Patents by Inventor Ka-Un Chan

Ka-Un Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224101
    Abstract: An inductor device includes a first wire, a second wire, and a third wire. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The sequence of the first sub-wires and the second sub-wires is that at least two first sub-wires of the first sub-wires and at least one second sub-wires of the second sub-wires are disposed to each other in an interlaced manner. The third wire is disposed adjacent to at least two first sub-wires of the first sub-wires.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 11, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 12205748
    Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes a first and a second sub-trace. The first sub-trace includes first wires, and the second sub-trace includes second wires. The second sub-trace is coupled to the first sub-trace at a first node. The first and the second wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The second trace includes a third and a fourth sub-trace. The third sub-trace includes third wires, and the fourth sub-trace includes fourth wires. The fourth sub-trace is coupled to the third sub-trace at a second node. The third and the fourth wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The capacitor is coupled between the first and the second node.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: January 21, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Hung-Han Chen, Ka-Un Chan
  • Patent number: 12205755
    Abstract: An inductor structure includes a first connecting component, a second connecting component, and a center-tap terminal. In the inductor structure, a first port of the first connecting component is coupled to a first wire, and a second port of the first connecting component is coupled to a second wire. The second connecting component disposed above or beneath the first connecting component in an interlaced manner. The center-tap terminal is coupled to one of the first connecting component and the second connecting component. The center-tap terminal is disposed on a layer that is different from the layer where the first connecting component is disposed or the layer where the second connecting component is disposed.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: January 21, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 12198846
    Abstract: An inductor device includes a first wire, a second wire, a third wire, a fourth wire and an 8-shaped inductor structure. The first wire is disposed in a first area. The second wire is disposed in a second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction. The third wire includes at least two third sub-wires, and the at least two third sub-wires are arranged with an interval between each other. The fourth wire is at least partially overlapped with the second wire in the vertical direction. The fourth wire includes at least two fourth sub-wires, and the at least two fourth sub-wires are arranged with an interval between each other. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 14, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 12176136
    Abstract: A transformer device includes a first coil, a second coil, and a third coil. The first coil includes a first ring structure, a second ring structure, a first connecting portion, and a first terminal, in which the first terminal is arranged on the first connecting portion and is located at a central location between the first ring structure and the second ring structure, the first terminal is connected to the first ring structure through the first connecting portion in a first direction, and connected to the second ring structure through the first connecting portion in a second direction, and the first direction is the opposite of the second direction. The second coil is configured to couple the first ring structure. The third coil is configured to couple the second ring structure, in which the second coil and the third coil have the same structure.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: December 24, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Jian-You Chen, Ka-Un Chan
  • Patent number: 12154708
    Abstract: An inductor device includes a first coil, a second coil and a toroidal coil. The first coil is partially overlapped with the second coil in a vertical direction. The toroidal coil is disposed outside the first coil and the second coil. The first coil is interlaced with the second coil at a first side and a second side of the inductor device.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 26, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 12112878
    Abstract: An asymmetric spiral inductor is provided. The asymmetric spiral inductor includes a first winding, a second winding and a third winding. The first winding has a first end and a second end and is implemented in the ultra-thick metal (UTM) layer of a semiconductor structure. The second winding, which has a third end and a fourth end, is implemented in the re-distribution layer of the semiconductor structure and has a first maximum trace width. The third winding, which has a fifth end and a sixth end, is implemented in the UTM layer of the semiconductor structure and has a second maximum trace width smaller than the first maximum trace width. The second and third ends are connected through a first through structure, the fourth and fifth ends are connected through a second through structure, and the first and sixth ends are the two ends of the asymmetric spiral inductor.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: October 8, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 12112875
    Abstract: An integrated circuit includes a first coil and a second coil. The first coil is disposed on the first side of the integrated circuit. The second coil is disposed on the second side of the integrated circuit, and is partially overlapped with the first coil at a junction. The first coil is not interlaced with the second coil at the junction.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: October 8, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Publication number: 20240312691
    Abstract: An inductor device includes a first trace, a second trace, a third trace, a fourth trace, and a double ring inductor. The first trace is disposed in a first area, and located on a first layer. The second trace is disposed in the first area, coupled to the first trace, and located on a second layer. The third trace is disposed in a second area, and located on the first layer. The fourth trace is disposed in the second area, coupled to the third trace, and located on the second layer. The double ring inductor is disposed on the first layer, located at outer side of the first trace and the third trace, and coupled to the first trace and the third trace.
    Type: Application
    Filed: May 23, 2024
    Publication date: September 19, 2024
    Inventors: Hsiao-Tsung YEN, Ka-Un CHAN
  • Patent number: 12094637
    Abstract: An inductor device includes a first inductor, a first connection member, a second inductor, and a second connection member. The first inductor includes a first and a second trace. The first trace is disposed in a first area, and the second trace is disposed in a second area. The first and the second area are connected at a junction. The first connection member is disposed at a block at which the first and the second trace are not disposed, and coupled to the first and the second trace. The second inductor includes a third and a fourth trace. The third trace is disposed in the first area, and the fourth trace is disposed in the second area. The second connection member is disposed at a block at which the third and the fourth trace are not disposed, and coupled to the third and the fourth trace.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: September 17, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ting-Yao Huang, Ka-Un Chan
  • Patent number: 12062480
    Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a first node. The second trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a second node. The capacitor is coupled to the firs node and the second node.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: August 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Jian-You Chen, Ka-Un Chan
  • Patent number: 12046403
    Abstract: A stacked inductor device including an 8-shaped inductor structure a stacked coil. The 8-shaped inductor structure includes a first coil and a second coil. The first coil is disposed in a first area. The first coil includes a first sub-coil and a second sub-coil, and the first sub-coil and the second sub-coil are disposed with an interval circularly with each other. The second coil is disposed in a second area, and the second coil is coupled with the first coil on a boundary between the first area and the second area. The second coil includes a third sub-coil and a fourth sub-coil, and the third sub-coil and the fourth sub-coil are disposed with an interval circularly with each other. The stacked coil is coupled to the first coil and the second coil and is stacked partially on or under the first coil and the second coil.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: July 23, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 12027298
    Abstract: An inductor device includes a first trace, a second trace, a third trace, a fourth trace, and a double ring inductor. The first trace is disposed in a first area, and located on a first layer. The second trace is disposed in the first area, coupled to the first trace, and located on a second layer. The third trace is disposed in a second area, and located on the first layer. The fourth trace is disposed in the second area, coupled to the third trace, and located on the second layer. The double ring inductor is disposed on the first layer, located at outer side of the first trace and the third trace, and coupled to the first trace and the third trace.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: July 2, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Publication number: 20240128306
    Abstract: An integrated transformer is provided. The integrated transformer includes a first inductor and second inductors. The first inductor includes a first winding having a first outer turn and a second winding having a second outer turn. The second inductor includes a third winding having a third outer turn and a fourth winding having a fourth outer turn. The first and third outer turns substantially overlap, and the second and fourth outer turns substantially overlap. The first and second outer turns are connected to each other through a first segment and a second segment that together form a crossing structure, and the third and fourth outer turns are connected to each other through a third segment and a fourth segment that together form a crossing structure. The first and third segments are in the first metal layer, while the second and fourth segments are in the second metal layer.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: HSIAO-TSUNG YEN, Ka-Un Chan
  • Patent number: 11949388
    Abstract: A power amplifier includes a power switching circuit, a driver circuit, and an amplifier circuit. The power switching circuit is configured to receive a first voltage and a second voltage, and provide the first voltage or the second voltage according to an operation mode of the power amplifier. The driver circuit is coupled to the power switching circuit. The driver circuit is configured to operate according to the first voltage or the second voltage and generate a driving signal according to an input signal. The amplifier circuit is coupled to the power switching circuit and the driver circuit. The amplifier circuit is configured to operate according to the first voltage or the second voltage and generate an output signal according to the driving signal.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 2, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Gen-Sheng Ran, Po-Chih Wang, Ka-Un Chan
  • Patent number: 11942906
    Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ting-Yao Huang, Teng-Yuan Chang, Po-Chih Wang, Ka-Un Chan
  • Patent number: 11942258
    Abstract: An inductor device includes a first and a second inductor and a first and a second connection member. A first and a second trace of the first inductor is located on a first and a second layer respectively. The second trace is coupled to the first trace located at a first and a second area. The first connection member is coupled to the second trace. A third and a fourth trace of the second inductor is located on the first and the second layer respectively. The first trace and the third trace are disposed in turn at the first area and the second area. The fourth trace is coupled to the third trace located at the first and the second area. The second and the fourth trace are disposed in turn at the first and the second area. The second connection member is coupled to the fourth trace.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: March 26, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ting-Yao Huang, Ka-Un Chan
  • Patent number: 11915848
    Abstract: An inductor device includes an 8-shaped inductor structure, a first spiral wire, a first connector, a second connector, and a first interlaced component. The 8-shaped inductor structure includes two first-wires and two second-wires. The first spiral wire is disposed on an inner side of the two first-wires. The first connector is coupled to one of the two first-wires and one of the two second-wires. The second connector is coupled to another one of the two first-wires. The first interlaced component is coupled to the first spiral wire and another one of the two second-wires, and the first interlaced component is coupled to the first connector and the second connector in an interlaced manner respectively.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 27, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 11901399
    Abstract: A semiconductor device includes a first coil, a second coil, and a third coil. The second coil is disposed with respect to the first coil. The third coil is configured to sense a signal on the first coil. A first overlapped area, on a projection plane, of the third coil and the first coil is larger than a second overlapped area, on the projection plane, of the third coil and the second coil.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 11901111
    Abstract: An inductor device includes a first wire, a second wire, at least one first connector, at least one second connector, and a first center-tapped terminal. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The first sub-wires and the second sub-wires are disposed in an interlaced manner. The at least one first connector couples the first sub-wire that is disposed on an outer side and the first sub-wire that is disposed on an inner side in the first sub-wires. The at least one second connector couples the second sub-wire that is disposed on the outer side and the second sub-wire that is disposed on the inner side in the second sub-wires. The first center-tapped terminal is coupled to the first sub-wire that is disposed on the outer side in the first sub-wires.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Kuan-Yu Shih, Ka-Un Chan