Abstract: An inductor device includes a first wire, a second wire, an input terminal, a third wire, a fourth wire, and an eight-shaped inductor structure. The first wire is disposed in a first area. The second wire is disposed in a second area. The input terminal is disposed on a first side of the second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction, in which the third wire is coupled to the first wire. The fourth wire is disposed in the second area and at least partially overlapped with the second wire in the vertical direction, in which the fourth wire is coupled to the second wire. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.

Abstract: A capacitor structure includes a first metal structure, a second metal structure, and a dielectric material. The second metal structure is disposed below the first metal structure. Each of the first metal structure and the second metal structure includes at least three conductive components. The conductive components have a fish-bone shape. The dielectric material is disposed in a plurality of isolators of the first metal structure, in a plurality of isolators of the second metal structure, and between the first metal structure and the second metal structure.

Abstract: A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

Abstract: An inductor device includes first, second, third and fourth wire, first and second connector, and eight-shaped inductor structure. First and second wires are disposed in first and second areas. Third wire is disposed in first area and partially overlapped with first wire in a vertical direction, and third wire is coupled to second wire. Fourth wire is disposed in second area and partially overlapped with second wire in the vertical direction, and fourth wire is coupled to first wire. First connector is partially overlapped with first wire or third wire in the vertical direction, and is coupled to inner wire and outer wire of third wire. Second connector is partially overlapped with second wire or fourth wire in the vertical direction, and is coupled to inner and outer wire of fourth wire. Eight-shaped inductor structure is disposed on outer side of third wire and fourth wire.

Abstract: A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.

Abstract: An operational amplifier includes a differential amplifier circuit and a common mode feedback circuit. The differential amplifier circuit includes a bias circuit, an amplifier circuit, and a load circuit. The bias circuit generates a first operation voltage. The amplifier circuit receives a pair of input signals, and generates a pair of output signals according to the input signals and the first operation voltage. The load circuit is coupled to the amplifier circuit. The common mode feedback circuit generates at least one common mode feedback voltage based on a common mode voltage and a reference voltage. The common mode voltage is associated with the output signals. The at least one common mode feedback voltage is for controlling the bias circuit and the load circuit, to control a direct current (DC) voltage level of the differential amplifier circuit.

Abstract: A semiconductor device is disposed below an inductor. The semiconductor device includes a metal-oxide-semiconductor capacitor structure and a patterned shielding structure. The metal-oxide-semiconductor capacitor structure includes a polysilicon layer, an oxide definition layer, and a first metal layer. The first metal layer is connected to the polysilicon layer and the oxide definition layer. The patterned shielding structure is disposed over the metal-oxide-semiconductor capacitor structure and includes a second metal layer.

Abstract: An oscillating signal generator circuit includes an oscillator circuit, a feedback circuit, and a voltage regulator circuit. The oscillator circuit is configured to generate a first and second oscillating signal at a first and second output terminal according to a first reference voltage. The first and second oscillating signals are a differential pair of signals. The oscillator circuit includes a common mode sensing circuit coupled between the first and second output terminals. The common mode sensing circuit is configured to sense a common mode component of the first and second oscillating signals so as to generate a sense voltage. The feedback circuit, coupled to the common mode sensing circuit, is configured to generate a feedback voltage according to the sense voltage. The voltage regulator circuit is coupled to the oscillator circuit and the feedback circuit, and configured to regulate a supply voltage so as to generate the first reference voltage.

Abstract: The invention discloses crossing structures of an integrated transformer or an integrated inductor. The crossing structures can be applied to various integrated transformers or integrated inductors. The crossing structures disclosed in the present invention includes multiple segments fabricated on a first metal layer of the semiconductor structure and multiple segments fabricated on a second metal layer of the semiconductor structure, the first metal layer being different from the second metal layer.

Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.

Abstract: A calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal. The processor is configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result. The present disclosure also provides a calibration method.

Abstract: A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

Abstract: A power amplifier includes a power switching circuit, a driver circuit, and an amplifier circuit. The power switching circuit is configured to receive a first voltage and a second voltage, and provide the first voltage or the second voltage according to an operation mode of the power amplifier. The driver circuit is coupled to the power switching circuit. The driver circuit is configured to operate according to the first voltage or the second voltage and generate a driving signal according to an input signal. The amplifier circuit is coupled to the power switching circuit and the driver circuit. The amplifier circuit is configured to operate according to the first voltage or the second voltage and generate an output signal according to the driving signal.

Abstract: An inductor device includes a first wire, a second wire, a third wire, a fourth wire, and an eight-shaped inductor structure. The first wire includes at least two first sub-wires. The second wire includes at least two second sub-wires. The third wire includes at least two third sub-wires. The fourth wire includes at least two fourth sub-wires. The first wire is disposed in a first area. The second wire is disposed in a second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction. The fourth wire is disposed in the second area and at least partially overlapped with the second wire in the vertical direction. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.

Abstract: An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.

Abstract: A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer. The shielding layer includes a first main portion and a plurality of branch portions. The first main portion is T-shaped. The branch portions are connected to the first main portion.

Abstract: An amplifier device includes a regulator circuit, a first voltage converting circuit, a first control circuit, and an amplifier circuit. The regulator circuit is configured to output a first driving voltage. The first voltage converting circuit is coupled to the regulator circuit, and is configured to output one of the first driving voltage and at least one first voltages related to the first driving voltage, as a first operating voltage. The first control circuit is coupled to the first voltage converting circuit through a first node, and is configured to receive the first operating voltage and generate a first operating signal according to the first operating voltage and a first control signal. The amplifier circuit is coupled to the first control circuit and the regulator circuit, and is configured to receive the first driving voltage, and is controlled by the first operating signal to generate an output voltage.

Abstract: An oscillating signal generator circuit includes an oscillator circuit, a feedback circuit, and a voltage regulator circuit. The oscillator circuit is configured to generate a first and second oscillating signal at a first and second output terminal according to a first reference voltage. The first and second oscillating signals are a differential pair of signals. The oscillator circuit includes a common mode sensing circuit coupled between the first and second output terminals. The common mode sensing circuit is configured to sense a common mode component of the first and second oscillating signals so as to generate a sense voltage. The feedback circuit, coupled to the common mode sensing circuit, is configured to generate a feedback voltage according to the sense voltage. The voltage regulator circuit is coupled to the oscillator circuit and the feedback circuit, and configured to regulate a supply voltage so as to generate the first reference voltage.

Abstract: An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

Abstract: A calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal. The processor is configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result. The present disclosure also provides a calibration method.