Abstract: A satellite signal receiving circuit includes an oscillator, two mixers, two phase shifters, two low-pass filters, two phase operation circuits, and a bandpass filter. When the frequency of the oscillator is between the center frequencies of the Global Orbiting Navigation Satellite System (GLONASS) and the GPS or the Galileo system, the GLONASS and GPS/Galileo satellite baseband signals are obtained through phase addition and subtraction performed by the phase operation circuits, while the BeiDou Navigation Satellite System (BDS) baseband signal is obtained through the bandpass filter. When the frequency of the oscillator is between the center frequencies of the BDS and the GPS or the Galileo system, the BDS and GPS/Galileo satellite baseband signals are obtained through phase addition and subtraction performed by the phase operation circuits, while the GLONASS satellite baseband signal is obtained through the bandpass filter.

Abstract: An output power linearization method, suitable for a calibration system, includes the following operations: providing an instruction signal, which corresponding to a currently ideal output power among multiple ideal output powers, to an emission module of the calibration system so that the emission module outputs a radio frequency (RF) signal with a practical output power according to the instruction signal; obtaining a feedback signal, by a feedback circuit of the calibration system, from an output terminal of the emission module, and calculating a feedback output power from the feedback signal; calculating an output difference between the currently ideal output power and the feedback output power; if an absolute value of the output difference is larger than an absolute value of a feedback error of the feedback circuit, adjusting a present gain of the emission module so that the practical output power approaches the currently ideal output power.

Abstract: An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.

Abstract: A transceiver device includes a digital baseband circuit, a first circuit portion, and a second circuit portion. The digital baseband circuit is configured to analyze power of an input signal, in order to generate a first control signal and a second control signal. The first circuit portion has a first gain, and is configured to be selected according to the first control signal to process the input signal to generate output signals. The second circuit portion has a second gain higher than the first gain, and is configured to be selected according to the second control signal to process the input signal to generate the output signals. The first circuit portion includes an N-way filter circuit, and the N-way filter circuit is configured to modulate the input signal according to first oscillating signals to perform a filtering operation.

Abstract: An inductor device includes a first wire, a second wire, and a third wire. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The sequence of the first sub-wires and the second sub-wires is that at least two first sub-wires of the first sub-wires and at least one second sub-wires of the second sub-wires are disposed to each other in an interlaced manner. The third wire is disposed adjacent to at least two first sub-wires of the first sub-wires.

Abstract: An output power linearization method, suitable for a calibration system, includes the following operations: providing an instruction signal, which corresponding to a currently ideal output power among multiple ideal output powers, to an emission module of the calibration system so that the emission module outputs a radio frequency (RF) signal with a practical output power according to the instruction signal; obtaining a feedback signal, by a feedback circuit of the calibration system, from an output terminal of the emission module, and calculating a feedback output power from the feedback signal; calculating an output difference between the currently ideal output power and the feedback output power; if an absolute value of the output difference is larger than an absolute value of a feedback error of the feedback circuit, adjusting a present gain of the emission module so that the practical output power approaches the currently ideal output power.

Abstract: A transceiver circuit includes a transceiver antenna, a transmitter circuit, a receiver circuit, a frequency synthesizer and a baseband circuit. The transmitter circuit transmits a radio frequency signal corresponding to a radio frequency through the transceiver antenna. The frequency synthesizer provides a first local oscillation signal and a second local oscillation signal having a first local oscillation frequency and a second local oscillation frequency, respectively. The baseband circuit operates in a transmitting mode and a receiving mode. In the transmitting mode, the frequency synthesizer provides the first local oscillation signal, and in the receiving mode, the frequency synthesizer provides the second local oscillation signal, the first local oscillation frequency is a non-integer multiple of the radio frequency, and the second local oscillation frequency is an integer multiple of the radio frequency.

Abstract: A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer. The shielding layer includes a first main portion and a plurality of branch portions. The first main portion is T-shaped. The branch portions are connected to the first main portion.

Abstract: An inductor device includes a first wire, a second wire, at least one first connector, at least one second connector, and a first center-tapped terminal. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The first sub-wires and the second sub-wires are disposed in an interlaced manner. The at least one first connector couples the first sub-wire that is disposed on an outer side and the first sub-wire that is disposed on an inner side in the first sub-wires. The at least one second connector couples the second sub-wire that is disposed on the outer side and the second sub-wire that is disposed on the inner side in the second sub-wires. The first center-tapped terminal is coupled to the first sub-wire that is disposed on the outer side in the first sub-wires.

Abstract: An asymmetric spiral inductor is provided. The asymmetric spiral inductor includes a first winding, a second winding and a third winding. The first winding has a first end and a second end and is implemented in the ultra-thick metal (UTM) layer of a semiconductor structure. The second winding, which has a third end and a fourth end, is implemented in the re-distribution layer of the semiconductor structure and has a first maximum trace width. The third winding, which has a fifth end and a sixth end, is implemented in the UTM layer of the semiconductor structure and has a second maximum trace width smaller than the first maximum trace width. The second and third ends are connected through a first through structure, the fourth and fifth ends are connected through a second through structure, and the first and sixth ends are the two ends of the asymmetric spiral inductor.

Abstract: Disclosed is an apparatus including a radio frequency amplifying circuit, a power supply circuit, and a bias generating circuit. The power supply circuit includes: a first power supply terminal coupled to a first ground terminal via a first capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a first switch; and a second power supply terminal coupled to a second ground terminal via a second capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a second switch, wherein the first capacitor and second capacitor are coupled to/decoupled from the radio frequency amplifying circuit through the first switch and second switch respectively, the supply voltages outputted from the two power supply terminals are different, and the two switches are not concurrently turned on. The radio frequency amplifying circuit operates according to a bias voltage provided by the bias generating circuit and one of the two supply voltages.

Abstract: A receiving device comprises a first receiving circuit, for receiving a plurality of signals and comparing a plurality of signal powers of the plurality of signals with a first threshold, to generate a first plurality of comparison results; a second receiving circuit, for receiving the plurality of signals and comparing the plurality of signal powers of the plurality of signals with a second threshold, to generate a second plurality of comparison results, wherein the first threshold is smaller than the second threshold; and a control circuit, coupled to the first receiving circuit and the second receiving circuit, for determining whether an average signal power of the plurality of signals is greater than a reference power according to the first plurality of comparison results and the second plurality of comparison results, to generate a determination result.

Abstract: A transceiver device includes a digital baseband circuit, a first circuit portion, and a second circuit portion. The digital baseband circuit is configured to analyze power of an input signal, in order to generate a first control signal and a second control signal. The first circuit portion has a first gain, and is configured to be selected according to the first control signal to process the input signal to generate output signals. The second circuit portion has a second gain higher than the first gain, and is configured to be selected according to the second control signal to process the input signal to generate the output signals. The first circuit portion includes an N-way filter circuit, and the N-way filter circuit is configured to modulate the input signal according to first oscillating signals to perform a filtering operation.

Abstract: A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.

Abstract: The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.

Abstract: A capacitor structure includes a first metal structure, a second metal structure, and a dielectric material. The second metal structure is disposed below the first metal structure. Each of the first metal structure and the second metal structure includes at least three conductive components. The conductive components have a fish-bone shape. The dielectric material is disposed in a plurality of isolators of the first metal structure, in a plurality of isolators of the second metal structure, and between the first metal structure and the second metal structure.

Abstract: A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer and a first stacked structure. The shielding layer extends along a plane. The first stacked structure is stacked, along a first direction, on the shielding layer. The first direction is perpendicular to the plane. The first stacked structure has a crossed shape and is configured to enhance a shielding effect.

Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a first node. The second trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a second node. The capacitor is coupled to the firs node and the second node.

Abstract: A semiconductor device includes a first coil, a second coil, and a third coil. The second coil is disposed with respect to the first coil. The third coil is configured to sense a signal on the first coil. A first overlapped area, on a projection plane, of the third coil and the first coil is larger than a second overlapped area, on the projection plane, of the third coil and the second coil.

Abstract: An inductor device includes first trace, second trace, third trace, fourth trace, first capacitor, and second capacitor. One terminal of each of the at least two sub-traces of first trace are coupled to each other at first node. One terminal of each of the at least two sub-traces of second trace are coupled to each other at second node. One terminal of third trace is coupled to second trace, and another terminal of third trace is coupled to first input/output terminal. One terminal of fourth trace is coupled to first trace, and another terminal of fourth trace is coupled to second input/output terminal. First capacitor is coupled to first node and second node. Second capacitor is coupled between firs node and first input/output terminal, or coupled between first node and second input/output terminal, or coupled between first input/output terminal and second input/output terminal.