Abstract: Disclosed is a semiconductor structure. The semiconductor structure includes a support structure, and a first dielectric layer and a growth substrate sequentially formed on the support structure, where a gravity center of the support structure and a gravity center of the growth substrate are disposed in a staggered manner, so that the direct contact between the growth substrate and the graphite disk can be avoided, a centrifugal force on the growth substrate exerted by the graphite disk to the support structure can be transferred, thereby further ensuring a quality of the growth substrate, and significantly reducing a probability of cracking to ensure a crystal quality of a subsequent epitaxial layer. The support structure is formed at the bottom of the growth substrate, so that a mechanical strength of the semiconductor structure can be effectively improved, a stability can be enhanced, and a deformation of the semiconductor structure can be suppressed.

Abstract: A semiconductor structure includes: a stacked structure, including one stacked structure unit or a plurality of stacked structure units disposed along a horizontal direction, where each of the stacked structure units includes a plurality of stacked island structures separated from each other along the horizontal direction; and an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially laminated on the stacked structure. In the present disclosure, by providing the stacked structure, the light-emitting efficiency of the semiconductor device can be improved.

Abstract: A substrate structure, a method for manufacturing a substrate structure, a light-emitting device and a method for manufacturing a light-emitting device are provided. The substrate structure may include a base, a mask layer, and an epitaxial structure. The mask layer is provided on the base, where the mask layer is provided with an opening for exposing the base. The epitaxial structure is provided in the opening, where a material of the mask layer is different from a material of the epitaxial structure.

Abstract: A method of manufacturing an electronic device including the following steps is provided herein. A plurality of first electronic components is provided. The plurality of first electronic components is transferred onto a plurality of pickup sites. An empty pickup site from the plurality of pickup sites may be figured out, wherein the plurality of first electronic components is absent at the empty pickup site. A second electronic component is transferred onto the empty pickup site. A target substrate is provided. The plurality of first electronic components and the second electronic component are transferred onto the target substrate.

Abstract: A semiconductor structure and a manufacturing method therefor are provided by embodiments of the present application. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. In the second buffer layer, by decreasing a doping concentration of the transition metal or not doping intentionally the transition metal, a tailing effect is avoided and current collapse is prevented. By doping periodically C in the buffer layer, C may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced.

Abstract: The present application provides a substrate and a manufacturing method therefor. The substrate includes a silicon substrate and a protective layer, the silicon substrate includes a middle part and an edge part, and a thickness of the middle part is greater than a thickness of the edge part. The middle part has a to-be-grown surface, and a crystal orientation of the to-be-grown surface is different from a crystal orientation of surface of the edge part. The protective layer covers the edge part and is configured to prevent defects in the edge part from extending to the middle part during high-temperature processing.

Abstract: An FPGA-based USB3.0/3.1 control system, including: a USB control module including a USB3.0 control module and/or a USB3.1 control module; a PCS logic module connected to the USB control module via a PIPE interface; an FPGA Serdes serial communication module connected to the PCS logic module; and an external daughter card module connected to the FPGA Serdes serial communication module, wherein the PCS logic module, the FPGA Serdes serial communication module and the external daughter card module are connected in sequence to achieve a port physical layer function for testing the USB 3.0 control module and the USB 3.1 control module. The control system solves the cumbersome problems of incomplete emulation verification, test mode limitations, and unchangeable hardware functions in the prior art.

Abstract: A manufacturing method of a vertical cavity surface emitting laser is provided. The vertical cavity surface emitting laser includes a first reflector, a first semiconductor layer, an active layer, a second semiconductor layer, an oxide layer, and a second reflector sequentially stacked. The conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer. The oxide layer includes a light transmitting region and a light shielding region, and the light shielding region surrounds the light transmitting region. The manufacturing method includes planarizing a first contact surface of the first semiconductor layer and the first reflector, and/or a second contact surface of the second semiconductor layer and the second reflector.

Abstract: A USB protocol-based IP infringement identification method for USB devices, including the following steps: S1, connecting an infringement identification device at a peer side of the USB host to be tested; S2, the USB host to be tested entering compliance mode; S3, the infringement identification device sending an X.LFPS file to the USB host to be tested; S4, upon the USB host to be tested receiving the X.LFPS file, the USB host to be tested sending IP copyright information to the infringement identification device; S5, determining whether the USB host to be tested infringes the IP. The infringement identification of the USB device to be tested is performed by using the compliance mode specified in the USB protocol, which is more stable, reliable and can also save costs.

Abstract: The present application provides method and circuit for monitoring a voltage of a power supply, which adopts a divided voltage circuit to obtain a divided voltage from an input voltage of an input power source generated from the power supply, for detecting the input voltage according to the divided voltage by adopting a first detection circuit and a second detection circuit. Also, judging whether the divided voltage is clamped according to a clamp threshold value to determine the first detection circuit or the second detection circuit detecting a detection current and determine another detection circuit detecting the divided voltage. Hereby, the input voltage transmitted from a rectification circuit to the power supply is monitored, and the dependence between the two detection circuits is avoided.

Abstract: A semiconductor structure and a manufacturing method thereof are provided in the present application provides. The semiconductor structure includes a substrate and a heterojunction structure located on the substrate. The heterojunction structure includes a channel layer and a barrier layer located on the channel layer. The channel layer includes at least one n-type doped layer. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a heterojunction structure on the substrate, where forming the heterojunction structure includes: forming a channel layer on the substrate, doping the channel layer to form an n-type doped layer; forming a barrier layer on the channel layer; forming a gate electrode, a source electrode and a drain electrode, the gate electrode is located on the heterojunction structure, and the source electrode and the drain electrode are located on two sides of the grid electrode, separately.

Abstract: Disclosed are an enhancement-mode switching device and a preparation method therefor. The enhancement-mode switching device includes: a substrate; a channel structure; an n-type semiconductor layer covering a bottom wall of the trench; a p-type semiconductor layer arranged in a gate region; a gate electrode arranged on a side, away from the substrate, of the p-type semiconductor layer; a source electrode arranged in a source region; a drain electrode arranged in a drain region. In the gate region, the p-type semiconductor layer and n-type semiconductor layer are in contact with each other to form a space depletion region in the gate region, and the electronic channel between the source electrode and the drain electrode of the switching device is interrupted, so that the switching device may be effectively turned off under a gate bias voltage of zero, improving control capability of the gate electrode and reliability of the device.

Abstract: The present disclosure provides enhancement mode switching devices and manufacturing methods thereof. The enhancement mode switching device includes a substrate; a channel structure including a channel layer and a barrier layer. The channel layer is provided on the substrate, and the barrier layer is provided on a side of the channel layer far away from the substrate. A side of the channel structure far away from the substrate is provided with a trench in a gate region, and the trench penetrates through the barrier layer and a part of the channel layer. The enhancement mode switching device includes a p-type semiconductor layer in the gate region, a gate electrode on a side of the p-type semiconductor layer far away from the substrate, a source electrode in the source region, and a drain electrode in the drain region. At least part of the p-type semiconductor layer is in the trench.

Abstract: A method of manufacturing an electronic device including the following steps is provided herein. A plurality of first electronic components is provided. The plurality of first electronic components is transferred onto a plurality of pickup sites. An empty pickup site from the plurality of pickup sites may be figured out, wherein the plurality of first electronic components is absent at the empty pickup site. A second electronic component is transferred onto the empty pickup site. A target substrate is provided. The plurality of first electronic components and the second electronic component are transferred onto the target substrate.

Abstract: The present disclosure provides a full-color LED structure, a full-color LED structure unit, and a method for manufacturing the same. Different wavelengths of light emitted from the first sub-region, the second sub-region and the third sub-region of the light-emitting layer are achieved by controlling different surface dimensions of the bottom wall and the side wall of the first trench or the top wall of the first semiconductor layer. The above process is simple and can form full-color LED structure units during a single epitaxial growth process of the light-emitting layer, such that the size of the full-color LED is reduced, the cost is reduced, the service life is extended, and the reliability is improved.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure, the mothed including: providing a substrate, a heterojunction structure, and a P-type semiconductor layer, which are distributed from bottom to top; forming a patterned mask layer on the P-type semiconductor layer, the patterned mask layer covering at least a portion of the P-type semiconductor layer in a gate region; removing an exposed portion of the P-type semiconductor layer by in-situ etching with a corrosive gas, by using the patterned mask layer as a mask; and then activating the P-type dopant ions in the P-type semiconductor layer.

Abstract: A switch control module for a switch mode power supply comprising a biased switch, an active switch and a control unit. The biased switch comprises a first node and a second node. The first node is coupled to a primary side winding. The active switch is connected to the second node. The control unit controls the ON/OFF states of the active switch and the biased switch is biased to be turned on initially. In this way, the active switch and the control unit are less likely to be damaged by voltage spikes generated by leakage in the primary side winding.

Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.

Abstract: The present disclosure provides a resonant tunneling diode including: a first barrier layer; a second barrier layer; a potential well layer between the first barrier layer and the second barrier layer, materials of the first barrier layer, the second barrier layer, and the potential well layer including a group III nitride, a material of the potential well layer including a gallium element; a first barrier layer between the first barrier layer and the potential well layer; and/or a second barrier layer between the second barrier layer and the potential well layer.

Abstract: The disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first group III nitride epitaxial layer disposed on a support substrate, a silicon substrate, a bonding layer and a second group III nitride epitaxial layer; wherein the first group III nitride epitaxial layer is bonded to the silicon substrate by the bonding layer; through-silicon-vias are formed in the silicon substrate, and first through-holes are formed in the bonding layer, wherein the through-silicon-vias communicate with the first through-holes; and the second group III nitride epitaxial layer is disposed within the first through-holes and the through-silicon-vias and on the silicon substrate, wherein the second group III nitride epitaxial layer is coupled to the first group III nitride epitaxial layer.