Abstract: In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and dummy nanostructures, forming lower source/drain regions, where lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source/drain regions; forming upper source/drain regions over the lower source/drain regions, where upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source/drain regions, forming a gate dielectric layer around the lower semiconductor nanostructures and the upper semiconductor nanostructures, forming a first metal-containing layer over the gate dielectric layer and around the lower semiconductor nanostructures, forming a second metal-containing layer over the first metal-containing layer and around the lower semiconductor nanostructures, and forming a third metal-containing layer over the gate dielectric layer and around the upper semico

Abstract: A method includes forming a semiconductor region, forming a gate spacer over the semiconductor region, forming a source/drain region aside of the semiconductor region, wherein the source/drain region is of p-type, and forming a gate dielectric over the semiconductor region. The gate dielectric is formed in a space between opposing portions of the gate spacer. A ruthenium oxide layer is formed over the gate dielectric, and acts as a part of a work-function layer of a gate electrode. The method further includes incorporating silicon into the ruthenium oxide layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

Abstract: A method includes providing a structure. The structure includes a stack of bottom channel layers, a stack of top channel layers disposed over the stack of bottom channel layers, an isolation feature sandwiched by the stack of bottom channel layers and the stack of bottom channel layers, and a first work function metal (WFM) layer wrapping around each of the bottom channel layers. The method further includes forming a second WFM layer wrapping around each of the top channel layers, forming a passivation layer on the second WFM layer by performing a gas treatment to the structure, and forming a metal fill layer over the passivation layer.

Abstract: A method includes forming a source/drain region, forming a contact etch stop layer over the source/drain region, forming an inter-layer dielectric over the contact etch stop layer, forming a first contact plug in the inter-layer dielectric and the contact etch stop layer, and performing an etching process to form a trench in the inter-layer dielectric and the contact etch stop layer. The source/drain region and the first contact plug are exposed to the trench. The method further includes performing a silicide formation process to form a silicide region on a surface of the source/drain region, and etching a metal layer that is deposited on dielectric regions and in the trench. The dielectric regions are exposed at a time the silicide formation process is started. A second contact plug is formed in the trench.

Abstract: A method includes forming a lower source/drain region and an upper source/drain region adjacent to a multi-layer stack, the multi-layer stack comprising dummy nanostructures that are alternatingly stacked with semiconductor nanostructures, the semiconductor nanostructures comprising lower semiconductor nanostructures and upper semiconductor nanostructures; removing the dummy nanostructures; forming first gate dielectrics around the lower semiconductor nanostructures and second gate dielectrics around the upper semiconductor nanostructures; forming a first work function metal layer over the first gate dielectrics and the second gate dielectrics; forming a first metal over the first work function metal layer; performing a first etch on the first metal to expose the first work function metal layer; performing a second etch on the first work function metal layer to expose the second gate dielectrics; forming a second work function metal layer over the second gate dielectrics; and forming a second metal over the s

Abstract: An exemplary stacked device structure includes a semiconductor layer stack disposed over a substrate and a dual work function metal (DWFM) gate. The semiconductor layer stack includes a first semiconductor layer disposed over a second semiconductor layer. The DWFM gate includes a first gate dielectric layer, a second gate dielectric layer, a first type work function metal layer, and a second type work function metal layer. The first gate dielectric layer is disposed over the first semiconductor layer, and the second gate dielectric layer is disposed over the second semiconductor layer. The first type work function metal layer is disposed over the first gate dielectric layer, and the second type work function metal layer is disposed over the second gate dielectric layer. At least one of the first type work function metal layer or the second type work function metal layer has a gradient composition.

Abstract: Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The structure includes a gate electrode layer disposed over a semiconductor layer, a source/drain region disposed adjacent the semiconductor layer, an interlayer dielectric (ILD) layer disposed over the source/drain region, a conductive feature disposed in the ILD layer over the source/drain region, a first dielectric layer disposed between the gate electrode layer and the conductive feature, a second dielectric layer distinct from the first dielectric layer disposed between the first dielectric layer and the gate electrode layer, a contact etch stop layer disposed between the second dielectric layer and the gate electrode layer, and a spacer disposed between the contact etch stop layer and the gate electrode layer.

Abstract: In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating semiconductor nanostructures and dummy nanostructures; forming lower source/drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source/drain regions; forming upper source/drain regions over the lower source/drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source/drain regions; removing the dummy nanostructures to form first openings between the lower semiconductor nanostructures, and second openings between the upper semiconductor nanostructures; forming a first metal-containing layer around the upper semiconductor nanostructures and in the second openings; exposing surfaces of the first metal-containing layer to a first molecular inhibitor to form a first passivation layer on the surfaces of the first metal-containing layer; and formin

Abstract: Complementary Field-Effect Transistors (CFETs) are formed having different combinations of work function metal layers that produce different threshold voltages. A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming third nanostructures over a third region of the substrate; depositing a first gate electrode layer on the first nanostructures; depositing a second gate electrode layer on the second nanostructures and on the first gate electrode layer on the first nanostructures; depositing a third gate electrode layer on the third nanostructures, on the second gate electrode layer on the second nanostructures, and on the second gate electrode layer on the first nanostructures; and depositing a fourth gate electrode layer on the third gate electrode layer, on the first nanostructures, on the second nanostructures, and on the third nanostructures.

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating semiconductor nanostructures and dummy nanostructures, forming lower source/drain regions, where lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source/drain regions, forming upper source/drain regions over the lower source/drain regions, where upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source/drain regions, removing the dummy nanostructures to form first openings between the lower semiconductor nanostructures, and second openings between the upper semiconductor nanostructures, forming a gate dielectric layer around the lower semiconductor nanostructures and the upper semiconductor nanostructures, forming a lower gate electrode around the lower semiconductor nanostructures and in the first openings, selectively depositing a dummy layer over top surfaces of the lower gate electrode, the dummy layer including a first polymer, a

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A method for predicting a communication strategy with patient, comprising: receiving a patient's demographic data; finding a model persona in a persona database based on the patient's demographic data; generating one or more first tasks based on a first communication strategy which meets attribute data of the model persona in the persona database; sending sequentially the one or more first tasks based on the first communication strategy to a client computer of the patient via a network; receiving sequentially one or more first responses with respect to the one or more first tasks from the client computer; and recording a first interaction history including the one or more first tasks and the corresponding one or more first responses in the persona database.

Abstract: A method for finding a timing of communication with respect to physiological information and associated timestamps is provided. The method comprising: receiving physiological measurement information of a first user from a sensing device via a network; obtaining a first timing of communication of first health specific information according to the physiological measurement information and corresponding timestamp; and transmitting the first health specific information to a client computer at the first timing.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

Abstract: An electrical connector includes: an insulating body; plural conductive terminals disposed in the insulating body, the conductive terminals including two signal terminals and one ground terminal arranged between the two signal terminals; a cable connected with the conductive terminals; and a metal shell disposed outside the insulating body, the metal shell including a top wall, an opening being set on the top wall, the shape of the opening being rectangular, the top wall being provided with elastic pieces protruding inward from the opening to electrically connect with the ground terminal, wherein the opening is sized and configured to achieve better electrical performance of the conductive terminals.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: Semiconductor structures and method of forming the same are provided. A method according to the present disclosure includes providing an intermediate structure that includes an opening, conformally depositing a metal liner over the opening, depositing a dummy fill material over the metal liner, recessing the dummy fill material such that a portion of the metal liner is exposed, removing the exposed portion of the metal liner, removing the recessed dummy fill material, and after the removing of the recessed dummy fill material, depositing a metal fill layer over the opening.

Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.