Abstract: An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.

Abstract: A triple locking hook connector includes a hook, a locking bar, a first spring, a controlling shaft, and a second spring. The hook has an axle hole and a first groove on an end of a hook opening, and has a spacing portion on the other end of the hook opening. An edge of an end of the locking bar has a first bolt. The first spring is to drive a first bolt to keep at the first position and to drive the other end of the locking bar to remain in the spacing portion. The controlling shaft joins the axle hole via a main axle to restrict the first bolt in the first position and to be driven by a second spring to stay at the third position to ensure the locking bar shutting the hook opening.

Abstract: A safety catch connector includes a catch member, first and second sleeves at two ends of the catch member to define a notch, a locking shaft slidably coupled at the first and second sleeves to selectively open and close the notch, a first controlling unit provided at the first sleeve to releasably lock up the locking shaft at the first sleeve, and a second controlling unit provided at the locking shaft to releasably lock up the locking shaft at the first sleeve, such that the first and second controlling units serves as two safety mechanisms to avoid an unintentional unlocking operation of the locking shaft. The locking shaft is quickly slid to open and close the notch for easy accessing.

Abstract: An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.

Abstract: An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.

Abstract: A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a channel region comprising dopants of a first type. The MOSFET device further includes a gate dielectric over the channel region, and a gate over the gate dielectric. The MOSFET device further includes a source comprising dopants of a second type, and a drain comprising dopants of the second type, wherein the channel region is between the source and the drain. The MOSFET device further includes a deactivated region underneath the gate, wherein dopants within the deactivated region are deactivated.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.

Abstract: A safety hook including a hook body, a latch member, a locking portion, and a control member is disclosed. The latch member is capable of rotating about a guide pin and swinging along a guide slot in an arc-shaped path to open or close a hook opening, wherein when the latch member locks and closes the hook opening, the locking portion and the guide pin form a locked chain structure to bear a lateral impact force on the latch member. When the latch member rotates about the guide pin and swings along the guide slot in an arc-shaped path to open or close the hook opening, the control member is capable of driving the locking edge to release the locking portion, so as to open the hook opening by a swinging movement of the latch member.

Abstract: The disclosure is directed to techniques for evaluating temporal quality of encoded video. Instead of estimating jerkiness based solely on frame rate or motion activity, the number of consecutive dropped frames forms a basic estimation unit. Several human visual system factors, such as sensitivity to temporal quality fluctuation and motion activity, have been taken into account to make the predicted jerkiness more consistent with the actual human visual response. The temporal quality metric can be used to estimate human perceived discomfort that is introduced by temporal discontinuity under various combinations of video shots, motion activity and local quality fluctuations. The techniques can be applied in two modes: (1) bitstream or (2) pixel mode. The quality metric can be used to evaluate temporal quality, or to control encoding or decoding characteristics to enhance temporal quality.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region.

Abstract: A system for displaying images including a touch display panel is provided. The touch display panel includes a first substrate. An electrode array is disposed on the first substrate, and the electrode array includes a first touch area. A first common electrode layer is disposed on the electrode array. A first dielectric layer is disposed between the electrode array and the first common electrode layer.

Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, first fins on the substrate, isolation regions on sides of the first fins, source/drain features on the substrate and dummy gate stacks separating the source/drain features on the substrate. The dummy gate stack is removed to expose the first fins and then the first fins are recessed to form channel trenches. A channel layer is deposited in the channel trenches and then is recessed. Then the isolation regions are recessed to laterally expose at least a portion of the recessed channel layer to form second fins. A high-k (HK) dielectric layer and a metal gate (MG) layer are deposited on the second fins.

Abstract: A stereo 3D video frame includes left and right components that are combined to produce a stereo image. For a given amount of distortion, the left and right components may have different impacts on perceptual visual quality of the stereo image due to asymmetry in the distortion response of the human eye. A 3D video encoder adjusts an allocation of coding bits between left and right components of the 3D video based on a frame-level bit budget and a weighting between the left and right components. The video encoder may generate the bit allocation in the rho (?) domain. The weighted bit allocation may be derived based on a quality metric that indicates overall quality produced by the left and right components. The weighted bit allocation compensates for the asymmetric distortion response to reduce overall perceptual distortion in the stereo image and thereby enhance or maintain visual quality.

Abstract: The present invention relates to an image display system with a touch panel sensing device, which applied in an electronic device, the touch panel sensing device including a substrate, a black matrix, a first planarizing layer, a conductive metal, vertical and horizontal electrode layers, a second planarization (PLN) layer, and a color resist layer disposed from top to bottom, wherein the vertical and horizontal electrode layers disposed between the first planarizing layer and the second PLN layer; therefore, by placing two perpendicularly electrode layers with the first planarizing layer on the same side, effectively to avoid chromatic aberration and reduce the thickness of the touch panel.

Abstract: An enhanced safety hook includes a hook body, a latch member, an operation handle and a spring member. The hook body includes a hook hole having a hook opening, a hook end formed at a top end thereof, a pin slot at a position below the hook opening, and a guide slot. The latch member includes a main plate and two side plates define an upside-down U-shape frame, a peripheral edge bridged between the two side plates in such a manner that a top end of the latch member constructs a mouth for receiving the hook end, a guide arm connected to the two side frames to couple with the guide slot, and a pin element coupling with the pin slot.

Abstract: A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.

Abstract: A capacitive touch panel and capacitance sensing apparatus and method for the same are disclosed. The capacitive touch panel includes a plurality of electrodes, a multiplexer and a capacitance sensing apparatus. The multiplexer selectively connects one of the electrodes to the capacitance sensing apparatus. The capacitance sensing apparatus includes a reference voltage source and a differential comparator, where the reference voltage source generates a modified reference voltage according to noise on stray capacitance of the capacitive touch panel. In a discharging process, the comparator compares an input voltage at the selected electrode and the modified reference voltage. The capacitance change in the electrode can be precisely detected because the noise is eliminated by differential comparison.