Abstract: A power failure prevention system and method with a power management mechanism are provided. A switch circuit is connected to a first terminal of an inductor. An energy storage circuit is connected to the switch circuit. A pre-charged circuit is connected to an input power source and a second terminal of the inductor. A pre-charging control circuit is connected to the pre-charged circuit and configured to obtain a voltage of a node between the pre-charged circuit and the second terminal of the inductor, a voltage of the switch circuit or a voltage of the energy storage circuit as a pre-charged voltage. The input power source pre-charges the pre-charged circuit. When the pre-charging control circuit determines that the pre-charged voltage is higher than or equal to a reference voltage, the pre-charging control circuit controls the pre-charged circuit, allowing the input power source to charge the energy storage circuit.

Abstract: A method includes obtaining a feature vector for each cell in a group of cells. The feature vector for a cell includes a score value for each feature in a set of features selected for characterizing the group of cells. The method includes clustering cells in the group into a selected number of clusters, based on distances between end points of feature vectors of the cells. The method includes generating a list of ranked critical cells in the selected number of clusters based on a list of prioritized features associated with the set of features. The method includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Abstract: An artificial intelligence accelerator receives a binary input data set and a selected layer of layers of overall weight pattern. The artificial intelligence accelerator includes processing tiles and a summation output circuit. Each processing tile receives one of input data subsets of the input data set and performs a convolution operation on weight blocks of each sub weight pattern of the overall weight pattern to obtain weight operation values and then obtains a weight output value expected from a direct convolution operation on the input data subset with the sub weight pattern through performing a multistage shifting and adding operation on the weight operation values. The summation output circuit sums up the plurality of weight output values through a multistage shifting and adding operation, so as to obtain a sum value expected from a direct convolution operation performed on the input data set with the overall weight pattern.

Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: The embodiments of the invention provide a multi-focal collimating lens and a headlight assembly for an automotive low beam. The multi-focal collimating lens includes a central collimating lens portion and two total internal reflection lens portions arranged on a left side and a right side of the central collimating lens portion. The central collimating lens portion and the total internal reflection lens portions share two focal points symmetrically located on both sides of a vertical symmetry plane of the multi-focal collimating lens. An upper edge and a lower edge of the multi-focal collimating lens are formed based on the two focal points, so that the headlight assembly is able to generate a cut-off line of the automotive low beam in a far-field light pattern of the multi-focal collimating lens.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure dividing the fin-shaped structure into a first portion and a second portion as the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion, a spacer around the top portion, a first epitaxial layer adjacent to one side of the top portion, and a second epitaxial layer adjacent to another side of the top portion.

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.

Abstract: An adaptive frequency adjusting system is provided. An error amplifier outputs an error amplified signal according to an output voltage of a power converter and a reference voltage. When a comparator determines that a voltage of a slope signal reaches a voltage of the error amplified signal within a maximum on-time of an upper bridge switch, the comparator outputs a reset signal. When the comparator determines that the voltage of the slope signal fails to reach the voltage of the error amplified signal and the maximum on-time ends, the comparator outputs the reset signal and instructs a clock generator to output a clock signal having a lower frequency. A driver circuit turns off the upper bridge switch and turns on a lower bridge switch according to the reset signal, and drives the upper bridge switch based on the clock signal having the lower frequency.

Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.