Patents by Inventor Kai Hsu

Kai Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF ANALYZING AND DETECTING CRITICAL CELLS
    Publication number: 20220198121
    Abstract: A method includes clustering cells in a group of cells into a selected number of clusters, and ranking the clusters based on a list of prioritized features to generate a list of ranked clusters. The method also includes ranking cells in each of one or more ranked clusters in the list of ranked clusters, based on the list of prioritized features, to generate a list of ranked critical cells. The method further includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Inventors: Anurag VERMA, Meng-Kai HSU, Chih-Wei CHANG
  • Semiconductor device and method for fabricating the same
    Patent number: 11355700
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: June 7, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • 3D SEPARABLE DEEP CONVOLUTIONAL NEURAL NETWORK FOR MOVING OBJECT DETECTION
    Publication number: 20220164630
    Abstract: A method for detecting moving objects in video frames, an apparatus and a non-transitory computer-readable storage medium thereof are provided. The method includes that: an encoder in a 3-dimenional (3D) separable convolutional neural network with multi-input multi-output (3DS_MM) receives a first input including multiple video frames, where the encoder includes a plurality of encoder layers including 3D separable convolutional neural network (CNN) layers; the encoder generates a first encoder output; and a decoder in the 3DS_MM receives the first encoder output and generates a first output including multiple first binary masks related to the first input, where the decoder includes a plurality of decoder layers comprising 3D separable transposed CNN layers.
    Type: Application
    Filed: November 22, 2021
    Publication date: May 26, 2022
    Applicants: KWAI INC., SANTA CLARA UNIVERSITY
    Inventors: Bingxin HOU, Ying LIU, Nam LING, Lingzhi LIU, Yongxiong REN, Ming Kai HSU
  • Disturbance source positioning method
    Patent number: 11340601
    Abstract: A disturbance source positioning method for positioning disturbance sources in a system including a plurality of nodes is provided. The method includes the following steps: grouping the plurality of nodes into a plurality of node groups based on an oscillation feature; establishing an in-group causality of the plurality of node groups based on a successive order of a coherent oscillation component; selecting at least one candidate group from the plurality of node groups based on the in-group causality; and positioning at least one disturbance source node in each candidate group.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 24, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Cheng Cheng, Chun-Yen Chen, Chen-Kai Hsu
  • Display device
    Patent number: 11335751
    Abstract: A display device includes: a substrate; a data line disposed on the substrate; an another data line disposed on the substrate and adjacent to the data line; a first light emitting diode including a first electrode; and a second light emitting diode including an another first electrode, wherein the first electrode partially overlaps the data line and the another first electrode partially overlaps the another data line.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 17, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Lien-Hsiang Chen, Kung-Chen Kuo, Sheng-Kai Hsu, Hsia-Ching Chu, Mei-Chun Shih
  • System and method for fluid separation
    Patent number: 11333017
    Abstract: This disclosure relates to a separating a fluid having multiple phases during formation testing. For example, certain embodiments of the present disclosure relate to receiving contaminated formation fluid on a first flow line and separating a contamination (e.g., mud filtrate) from the formation fluid by diverting the relatively heavier and/or denser fluid (e.g., the mud filtrate) downward through a second flow line and diverting the relatively lighter and/or less dense fluid upward through a third flow line. In some embodiments, the third flow line is generally oriented upwards at a height that may facilitate the separation of the heavier fluid from the relatively lighter fluid based on gravity and/or pumps.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: May 17, 2022
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Thomas Pfeiffer, Ashers Partouche, Kai Hsu, Simon Edmundson
  • Inference operation method and controlling circuit of 3D NAND artificial intelligence accelerator
    Patent number: 11309028
    Abstract: An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: April 19, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Kai Hsu, Teng-Hao Yeh
  • Semiconductor Device
    Publication number: 20220115587
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
    Type: Application
    Filed: November 5, 2020
    Publication date: April 14, 2022
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20220115584
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Application
    Filed: November 3, 2020
    Publication date: April 14, 2022
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Counting method for counting the stage number passing through a signal path on a graphical user interface
    Patent number: 11301606
    Abstract: A counting method adapted to count the stage number of an integrated circuit is provided herein. The counting method includes selecting an initial segment on a graphical user interface; determining whether the initial segment is floating; when it is determined that the initial segment is coupled to a first device, storing the first device in a device register; increasing the stage number by 1 to be a first stage number corresponding to the first device; storing all segments coupled to the first device except the initial segment in a first coupling register; selecting a first segment from the first coupling register; determining whether the first segment is floating; and when it is determined that the first segment is not floating, displaying the first stage number at the first segment on the graphical user interface.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: April 12, 2022
    Assignee: WINDBOND ELECTRONICS CORP.
    Inventor: Kai-Hsu Cheng
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20220102621
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Application
    Filed: November 1, 2020
    Publication date: March 31, 2022
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Method of analyzing and detecting critical cells
    Patent number: 11288436
    Abstract: A method includes obtaining a feature vector for each cell in a group of cells. The feature vector for a cell includes a score value for each feature in a set of features selected for characterizing the group of cells. The method includes clustering cells in the group into a selected number of clusters, based on distances between end points of feature vectors of the cells. The method includes generating a list of ranked critical cells in the selected number of clusters based on a list of prioritized features associated with the set of features. The method includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anurag Verma, Meng-Kai Hsu, Chih-Wei Chang
  • In-memory multiply-add computing device adapted to process input signals with improved accuracy
    Patent number: 11289152
    Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: March 29, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ming-Liang Wei, Po-Kai Hsu, Hang-Ting Lue, Teng-Hao Yeh
  • STRUCTURE OF HIGH-VOLTAGE TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20220093798
    Abstract: The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.
    Type: Application
    Filed: October 16, 2020
    Publication date: March 24, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Chun-Ya Chiu, Chih-Kai Hsu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20220093742
    Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.
    Type: Application
    Filed: October 27, 2021
    Publication date: March 24, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • METHOD FOR FABRICATING HIGH-VOLTAGE (HV) TRANSISTOR
    Publication number: 20220093411
    Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Jung Hsu, Chun Yu Chen, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • STRUCTURE OF SEMICONDUCTOR DEVICE
    Publication number: 20220093741
    Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.
    Type: Application
    Filed: October 27, 2021
    Publication date: March 24, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220085210
    Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.
    Type: Application
    Filed: October 12, 2020
    Publication date: March 17, 2022
    Inventors: Chang-Po Hsiung, Ching-Chung Yang, Shan-Shi Huang, Shin-Hung Li, Nien-Chung Li, Wen-Fang Lee, Chiu-Te Lee, Chih-Kai Hsu, Chun-Ya Chiu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Switch seat body structure
    Patent number: 11276534
    Abstract: A switch seat body structure includes a main body for assembling with a switch component. The main body is composed of a metal head section in the form of a thin sheet structure and a nonmetal belly section. The main body is defined with an axis. The metal head section has a first wall normal to or inclined from the axis and a second wall connected with the first wall and parallel to or inclined from the axis. The first and second walls together define a space. The nonmetal belly section fills the space to connect with entire sections of the first and second walls as an integrated body. The switch seat body assembling structure improves the problems that the processing and manufacturing processes are time-consuming and troublesome and the material cost is higher.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 15, 2022
    Assignees: Switchlab Inc., Switchlab (Shanghai) Co., Ltd., Gaocheng Electronics Co., Ltd.
    Inventors: Chih-Yuan Wu, Chih-Hao Sung, Chih-Kai Hsu
  • INFERENCE OPERATION METHOD AND CONTROLLING CIRCUIT OF 3D NAND ARTIFICIAL INTELLIGENCE ACCELERATOR
    Publication number: 20220068387
    Abstract: An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 3, 2022
    Inventors: Po-Kai HSU, Teng-Hao YEH