Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.

Abstract: The disclosure provides for a method for setting an inflatable packer. The method includes positioning an inflatable packer within a borehole, and pumping fluid into an inflatable element of the inflatable packer using a pump that is driven by a motor. The method includes measuring pressure of the inflatable element, determining a derivative of the measured pressure with respect to time, and determining onset of restraining of the inflatable element has occurred. Upon or after determining the onset of restraining, the method includes turning off the motor or slowing down an rpm of the motor. The disclosure also provides for a system, including a computer readable medium with processor-executable instructions stored thereon that are configured to instruct a processor to execute a pressure control algorithm to control a speed of the motor in response to pressure measurement data from the pressure sensor.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.

Abstract: A semiconductor apparatus includes a first cell having a first interconnect structure and a second cell having a second interconnect structure. The semiconductor apparatus further includes a first plurality of conductive segments, wherein each conductive segment of the first plurality of conductive segments directly connects a first metal level of the first interconnect structure to a first metal level of the second interconnect structure. The semiconductor apparatus further includes a third cell having a third interconnect structure and a fourth cell having a fourth interconnect structure. The semiconductor apparatus further includes a second plurality of conductive segments, wherein each conductive segment of the second plurality of conductive segments directly connects a second metal level of the third interconnect structure to a second metal level of the fourth interconnect structure, and the second metal level is different from the first metal level.

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

Abstract: A display device includes: a substrate; a data line disposed on the substrate; an another data line disposed on the substrate and adjacent to the data line; a first light emitting diode including a first electrode; and a second light emitting diode including an another first electrode, wherein the first electrode partially overlaps the data line and the another first electrode partially overlaps the another data line.

Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.

Abstract: A method for live migration of a virtual machine in a MR-IOV environment is provided. The method is used in a system, wherein the system includes a plurality of computing hosts, an MR-IOV device, and a management host including a physical function and configured to implement a plurality of virtual functions. Eand each computing host and the management host are coupled to the MR-IOV device. The method includes: migrating, by a source computing host of the computing hosts, a source virtual machine in the source computing host to a destination VM in a destination computing host of the computing hosts, wherein the source VM includes a source VF; transmitting, by the destination computing host, a request message to a management host and reassigning, by the management host, a first VF corresponding to the source VF in the management host to the destination VM according to the request message.

Abstract: A hub device and a power supply method thereof are provided. The hub device includes a power input port, first and second power output ports, a power management circuit and a controller. When first and second electronic devices are respectively connected to the first and second power output ports, the controller determines an input electric power from at least one default supply power of the power adapter based on first operating power information of the first electronic device and second operating power information of the second electronic device, so as to control the power adapter to provide the input electric power to the power input port. The power management circuit receives the input electric power to generate first and second operating power, so as to output the first operating power to the first power output port and output the second operating power to the second power output port.

Abstract: This disclosure relates to a separating a fluid having multiple phases during formation testing. For example, certain embodiments of the present disclosure relate to receiving contaminated formation fluid on a first flow line and separating a contamination (e.g., mud filtrate) from the formation fluid by diverting the relatively heavier and/or denser fluid (e.g., the mud filtrate) downward through a second flow line and diverting the relatively lighter and/or less dense fluid upward through a third flow line. In some embodiments, the third flow line is generally oriented upwards at a height that may facilitate the separation of the heavier fluid from the relatively lighter fluid based on gravity and/or pumps.

Abstract: A method for measuring asphaltene content of a crude oil is provided. In one embodiment, the method includes measuring an optical density of a live crude oil within a well and calculating a formation volume factor of the live crude oil based on the measured optical density. The method also includes determining asphaltene content of the live crude oil based on the measured optical density and the calculated formation volume factor of the live crude oil. Additional methods, systems, and devices are also disclosed.

Abstract: The present invention is related to a method for treating and/or preventing Alzheimer's disease, especially using mitochondria for treatment and/or prevention of Alzheimer's disease.

Abstract: A display device is disclosed, which includes: a first substrate; a first data line disposed on the first substrate; a first electrode disposed on the first substrate; and a first pixel defining layer disposed on the first electrode, wherein the first pixel defining layer exposes a part of the first electrode to define a first light emitting region, wherein, in a normal direction view of the first substrate, the first light emitting region partially overlaps the first data line.

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

Abstract: A switch seat body structure includes a main body for assembling with a switch component. The main body is composed of a metal head section in the form of a thin sheet structure and a nonmetal belly section. The main body is defined with an axis. The metal head section has a first wall normal to or inclined from the axis and a second wall connected with the first wall and parallel to or inclined from the axis. The first and second walls together define a space. The nonmetal belly section fills the space to connect with entire sections of the first and second walls as an integrated body. The switch seat body assembling structure improves the problems that the processing and manufacturing processes are time-consuming and troublesome and the material cost is higher.