Abstract: A switch seat body assembling structure includes a main body for assembling with a switch component. The main body is composed of a metal head section in the form of a thin sheet structure and a nonmetal belly section. The main body is defined with an eccentric axis and has a shaft hole positioned on the eccentric axis. The metal head section has a first wall normal to or inclined from the eccentric axis and a second wall connected with the first wall and parallel to or inclined from the eccentric axis. The first and second walls together define a space. The nonmetal belly section fills the space to connect with entire sections of the first and second walls as an integrated body. The switch seat body assembling structure improves the problems that the processing and manufacturing processes are time-consuming and troublesome and the material cost is higher.

Abstract: Methods for treating a wound or promote wound healing are provided, comprising the step of administering a composition including an effective amount of ?-1 adrenergic receptor antagonist to a subject in need thereof. Also provided is apparatus for wound healing, comprising a dressing and a composition including an effective amount of ?-1 adrenergic receptor antagonist.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

Abstract: A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

Abstract: An adaptive frequency adjusting system is provided. An error amplifier outputs an error amplified signal according to an output voltage of a power converter and a reference voltage. When a comparator determines that a voltage of a slope signal reaches a voltage of the error amplified signal within a maximum on-time of an upper bridge switch, the comparator outputs a reset signal. When the comparator determines that the voltage of the slope signal fails to reach the voltage of the error amplified signal and the maximum on-time ends, the comparator outputs the reset signal and instructs a clock generator to output a clock signal having a lower frequency. A driver circuit turns off the upper bridge switch and turns on a lower bridge switch according to the reset signal, and drives the upper bridge switch based on the clock signal having the lower frequency.

Abstract: A method includes positioning a downhole acquisition tool in a wellbore in a geological formation. The method includes operating a pump module to gather information for a fluid outside of the downhole acquisition tool that enters the downhole acquisition tool from a first flowline, a second flowline, or both while the downhole acquisition tool is within the wellbore. Operating the pump module includes controlling a valve assembly to a first valve configuration that enables the fluid to flow into the downhole tool via the first flowline fluidly coupled to a first pump module.

Abstract: A memory apparatus and compensation method for a computation result thereof are provided. The memory apparatus includes a memory sub-block, a reference memory sub-block and a control circuit. During a computation phase, the memory sub-block receives an input signal, and generates a computation result by a multiply-accumulate operation according to the input signal. The reference memory sub-block includes a plurality of memory cells pre-programmed with a reference weight value. The reference memory sub-block receives a reference input signal during a calibration phase, and generates a reference computation value by a multiply-accumulate operation according to the reference input signal and the reference weight value. The control circuit generates an adjustment value according to the reference computation value and a standard computation value, and during the computation phase, adjusts the computation result according to the adjustment value to generate an adjusted computation result.

Abstract: A display device includes a plurality of LCD displays, a plurality of LED strips, an image splitter, an image extractor, and a driving circuit. Each of the LCD displays displays corresponding split data. The LED strips are disposed among the LCD displays. Each of the LED strips displays patch data according to a corresponding driving signal. The LCD displays and the LED strips form a display wall to display image data. The image splitter splits the image data to generate the split data. The screen extractor generates the patch data according to the image data. The driving circuit generates the driving signals according to the patch data.

Abstract: A charger having a fast transient response and a control method thereof are provided, which decide how to quickly respond to a requirement of a load by determining whether an input current reference signal indicating an input current is larger than or equal to a maximum safe current of a transformer. Therefore, the charger and the control method realize the fast transient response without having to control switching between a boost circuit and a buck circuit. Meanwhile, the charger and the control method thereof can be prevented from being damaged by an excessive input current and can stabilize an output voltage of the load more quickly.

Abstract: A power failure prevention system and method with a power management mechanism are provided. A switch circuit is connected to a first terminal of an inductor. An energy storage circuit is connected to the switch circuit. A pre-charged circuit is connected to an input power source and a second terminal of the inductor. A pre-charging control circuit is connected to the pre-charged circuit and configured to obtain a voltage of a node between the pre-charged circuit and the second terminal of the inductor, a voltage of the switch circuit or a voltage of the energy storage circuit as a pre-charged voltage. The input power source pre-charges the pre-charged circuit. When the pre-charging control circuit determines that the pre-charged voltage is higher than or equal to a reference voltage, the pre-charging control circuit controls the pre-charged circuit, allowing the input power source to charge the energy storage circuit.

Abstract: A method includes obtaining a feature vector for each cell in a group of cells. The feature vector for a cell includes a score value for each feature in a set of features selected for characterizing the group of cells. The method includes clustering cells in the group into a selected number of clusters, based on distances between end points of feature vectors of the cells. The method includes generating a list of ranked critical cells in the selected number of clusters based on a list of prioritized features associated with the set of features. The method includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Abstract: An artificial intelligence accelerator receives a binary input data set and a selected layer of layers of overall weight pattern. The artificial intelligence accelerator includes processing tiles and a summation output circuit. Each processing tile receives one of input data subsets of the input data set and performs a convolution operation on weight blocks of each sub weight pattern of the overall weight pattern to obtain weight operation values and then obtains a weight output value expected from a direct convolution operation on the input data subset with the sub weight pattern through performing a multistage shifting and adding operation on the weight operation values. The summation output circuit sums up the plurality of weight output values through a multistage shifting and adding operation, so as to obtain a sum value expected from a direct convolution operation performed on the input data set with the overall weight pattern.

Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: The embodiments of the invention provide a multi-focal collimating lens and a headlight assembly for an automotive low beam. The multi-focal collimating lens includes a central collimating lens portion and two total internal reflection lens portions arranged on a left side and a right side of the central collimating lens portion. The central collimating lens portion and the total internal reflection lens portions share two focal points symmetrically located on both sides of a vertical symmetry plane of the multi-focal collimating lens. An upper edge and a lower edge of the multi-focal collimating lens are formed based on the two focal points, so that the headlight assembly is able to generate a cut-off line of the automotive low beam in a far-field light pattern of the multi-focal collimating lens.