Abstract: A method of semiconductor die singulation is provided. The method includes forming a first trench along a singulation lane of a semiconductor wafer. A second trench is formed extending from a bottom of the first trench. A portion of the semiconductor wafer remains between a bottom of the second trench and a backside of the semiconductor wafer. A cut is formed by way of a laser to singulate die of the semiconductor wafer. The cut extends through the portion of the semiconductor wafer remaining between the bottom of the second trench and the backside of the semiconductor wafer.

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: The disclosure provides for a method for setting an inflatable packer. The method includes positioning an inflatable packer within a borehole, and pumping fluid into an inflatable element of the inflatable packer using a pump that is driven by a motor. The method includes measuring pressure of the inflatable element, determining a derivative of the measured pressure with respect to time, and determining onset of restraining of the inflatable element has occurred. Upon or after determining the onset of restraining, the method includes turning off the motor or slowing down an rpm of the motor. The disclosure also provides for a system, including a computer readable medium with processor-executable instructions stored thereon that are configured to instruct a processor to execute a pressure control algorithm to control a speed of the motor in response to pressure measurement data from the pressure sensor.

Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A transient response improving system and method with a prediction mechanism of an error amplified signal are provided. A current sensor circuit senses a current flowing through a first resistor connected between an adapter and an electronic device. When the current is larger than a current threshold, a predicting circuit calculates a target voltage level based on a common voltage and a voltage of the battery and instantly pulls up or down a voltage level of the error amplified signal to the target voltage level. A comparator compares the error amplified signal with a ramp signal to output a comparison signal. A controller circuit controls a driver circuit to switch a high-side switch and a low-side switch according to the comparison signal.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

Abstract: A three dimension memory device and a ternary content addressable memory cell are provided. The ternary content addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND type flash memory line. The second memory cell is disposed in a second AND type flash memory line. The first search switch is coupled between a first bit line corresponding to the first AND type flash memory line and a match line, and is controlled by a first search signal to be turned on or cut off. The second search switch is coupled between a second bit line corresponding to the second AND type flash memory line and the match line, and is controlled by a second search signal to be turned on or cut off.

Abstract: Embodiments present a method for fluid type identification from a downhole fluid analysis that uses machine learning techniques that are trained and derived from a computer model using pressure, temperature and downhole optical characteristics of sampled fluid. The method comprises collecting optical spectral data for a downhole fluid; providing the collected optical spectral data to a trained classification module; processing the collected optical spectral data with the trained classification module configured to determine a fluid type classification; and determining a fluid type based upon the classification based upon the trained classification module.

Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

Abstract: The present disclosure provides an adapter assembly. Portion of the main body of the plug adapter is penetrated through the opening and exposed to the exterior of the accommodation space. Each protrusion is penetrated through the concave and exposed to the exterior of the accommodation space. Each protrusion exposed to the exterior of the accommodation space is connected with the position-limiting portion through the rotation of the plug adapter. Each fastening element is plugged into the first hole and the second hole. The plug adapter is fastened to the casing through the fastening element and the connection between the protrusion and the position-limiting portion. The adapter assembly includes two impact bearing points. One is formed by the fastening element, and the other is formed by the connection between the protrusion and the position-limiting portion. The stability and the waterproof capability of the adapter assembly are enhanced.

Abstract: The present disclosure provides an adapter assembly. Portion of the main body of the plug adapter is penetrated through the opening and exposed to the exterior of the accommodation space. Each protrusion is penetrated through the concave and exposed to the exterior of the accommodation space. Each protrusion exposed to the exterior of the accommodation space is connected with the position-limiting portion through the rotation of the plug adapter. Each fastening element is plugged into the first hole and the second hole. The plug adapter is fastened to the casing through the fastening element and the connection between the protrusion and the position-limiting portion. The adapter assembly includes two impact bearing points. One is formed by the fastening element, and the other is formed by the connection between the protrusion and the position-limiting portion. The stability and the waterproof capability of the adapter assembly are enhanced.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: A layout method and a semiconductor device are disclosed. The layout method includes: generating a design layout by placing a cell, wherein the cell includes: a first conductive segment overlapping a source/drain region and disposed immediately adjacent to a first power rail, wherein the first conductive segment has a length substantially equal to a cell length; a second conductive segment; and a third conductive segment between the first and second conductive segments. The layout method further includes: providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments are aligned in a first direction.

Abstract: Aspects of the invention relate to a keyboard key structure, a light guide for the keyboard key structure, and a computer key mechanism. The keyboard key structure can include a substrate; a key switch where the bottom of the key switch is configured to be coupled to the substrate; a keycap including a transparent region; a light guide coupled to the side of the key switch, the light guide comprising: a planar bottom surface and a planar top surface that is wider than and parallel to the bottom surface; a light emitting element coupled to the substrate and configured under the bottom surface of the light guide such that the light emitting element, the light guide, and the transparent region of the key cap are in a collinear arrangement.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: A video-image-interpolation apparatus is provided, which includes at least three image-layering circuits, at least three motion-estimation circuits, a motion-estimation-filtering circuit, a motion-compensated frame-interpolation circuit, and a display-control circuit. Each motion-estimation circuit performs motion estimation on a reference image-layer sequence and a reference subtitle-layer sequence that are generated from an input video signal by each image-layering circuit. The motion-estimation-filtering circuit adaptively determines the motion-estimation circuit having the smallest motion error.