Patents by Inventor Kai Jen

Kai Jen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210170482
    Abstract: A method for manufacturing a metal object having a solid lubricating surface layer includes: providing a metal blank having a surface; providing a plurality of microparticles and solid lubricating powder, and mixing them together, wherein the microparticles have a hardness greater than that of the surface; and projecting the microparticles and the solid lubricating powder onto the surface, wherein the microparticles cause plastic flow on the surface to form a compressive stress layer, and the solid lubricating powder adheres to the compressive stress layer to form a solid lubricating surface layer.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 10, 2021
    Inventors: TSENG-JEN CHENG, KAI-HAN CHEN, FU-CHUAN HSU, CHIH-HAO LIN
  • Patent number: 11032914
    Abstract: A method of forming a solderable solder deposit on a contact pad, comprising the steps of providing an organic, non-conductive substrate which exposes said contact pad under an opening of a first non-conductive resist layer, depositing a conductive layer inside and outside the opening such that an activated surface results, thereby forming an activated opening, electrolytically depositing nickel or nickel alloy into the activated opening such that nickel/nickel alloy is deposited onto the activated surface, electrolytically depositing tin or tin alloy onto the nickel/nickel alloy, with the proviso that the electrolytic deposition of later steps results in an entirely filled activated opening, wherein the entirely filled activated opening is completely filled with said nickel/nickel alloy, or in the entirely filled activated opening the total volume of nickel/nickel alloy is higher than the total volume of tin and tin alloy, based on the total volume of the entirely filled activated opening.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 8, 2021
    Assignee: Atotech Deutschland GmbH
    Inventors: Kai-Jens Matejat, Sven Lamprecht, Jan Sperling, Christian Ohde
  • Publication number: 20210164965
    Abstract: A method of characterizing a serum or plasma portion of a specimen in a specimen container includes capturing a plurality of images of the specimen container from multiple viewpoints, stacking the multiple viewpoint images along a channel dimension into a single stacked input, and processing the stacked input with a single deep convolutional neural network (SDNN). The SDNN includes a segmentation convolutional neural network that receives the stacked input and outputs multiple label maps simultaneously. The SDNN also includes a classification convolutional neural network that processes the multiple label maps and outputs an HILN determination (Hemolysis, Icterus, and/or Lipemia, or Normal) of the serum or plasma portion of the specimen. Quality check modules and testing apparatus configured to carry out the method are also described, as are other aspects.
    Type: Application
    Filed: June 10, 2019
    Publication date: June 3, 2021
    Applicant: Siemens Healthcare Diagnostics Inc.
    Inventors: Kai Ma, Yao-Jen Chang, Terrence Chen, Benjamin S. Pollack
  • Patent number: 11026022
    Abstract: The disclosure provides an audio signal processing circuit and an audio signal processing method, adapted for processing the input signal of a speaker configured with a rated power. The audio signal processing circuit includes, but not limited to, an audio signal generator and a power adjuster. The audio signal generator provides an audio signal including a high-frequency signal and a middle and low-frequency signal. The power adjuster is electronically coupled to the audio signal generator, and adjusts the power of the high-frequency signal according to an enhanced power larger than the rated power without adjusting the power of the middle and low-frequency signal. The output signal of the power adjuster can be inputted into the speaker. Accordingly, the transmission range for the high-frequency signal can be improved.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Acer Incorporated
    Inventors: Po-Jen Tu, Jia-Ren Chang, Kai-Meng Tzeng
  • Patent number: 11018140
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 25, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yi-Hao Chien, Kazuaki Takesako, Kai Jen, Hung-Yu Wei
  • Patent number: 11019439
    Abstract: An adjusting system and an adjusting method for equalization processing are provided. Frequency band energies of sound receiving signals are obtained. The frequency band energies correspond to different frequency bands, respectively. Target gains corresponding to frequency bands are determined according to the frequency band energies. Frequency responses of filtering processing with respect to a plurality of center frequencies are obtained. Equalization gains corresponding to the frequency bands and having the least gain error are determined. The gain error is related to a difference between the amplitude obtained after the equalization gains are reflected on the frequency responses corresponding to the filtering processing and the target gains. The equalization gains are inputted into the filtering processing according to the corresponding frequency bands. Accordingly, the impact of the filtering processing can be reduced.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 25, 2021
    Assignee: Acer Incorporated
    Inventors: Po-Jen Tu, Jia-Ren Chang, Kai-Meng Tzeng
  • Publication number: 20210152934
    Abstract: The disclosure provides an audio signal processing circuit and an audio signal processing method, adapted for processing the input signal of a speaker configured with a rated power. The audio signal processing circuit includes, but not limited to, an audio signal generator and a power adjuster. The audio signal generator provides an audio signal including a high-frequency signal and a middle and low-frequency signal. The power adjuster is electronically coupled to the audio signal generator, and adjusts the power of the high-frequency signal according to an enhanced power larger than the rated power without adjusting the power of the middle and low-frequency signal. The output signal of the power adjuster can be inputted into the speaker. Accordingly, the transmission range for the high-frequency signal can be improved.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 20, 2021
    Applicant: Acer Incorporated
    Inventors: Po-Jen Tu, Jia-Ren Chang, Kai-Meng Tzeng
  • Publication number: 20210151580
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Publication number: 20210152256
    Abstract: An image transmission system is disclosed. The image transmission system includes at least one image capturing device, at least one conversion device, at least one image processor, and at least one flexible printed circuit (FPC). The at least one FPC includes at least one conductive layer and at least one optical waveguide layer. The at least one image capturing device is configured to capture at least one data. The at least one conversion device is configured to perform a conversion between the at least one data and an optical signal. The at least one image processor is configured to obtain the at least one data according to the optical signal, and processes the data. The at least one optical waveguide layer is configured to transmit the optical signal.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 20, 2021
    Inventors: Po-Kuan SHEN, Chao-Chieh HSU, Chun-Chiang YEN, Chiu-Lin YU, Kai-Lun HAN, Sheng-Fu LIN, Jenq-Yang CHANG, Mao-Jen WU
  • Patent number: 11012800
    Abstract: A correction system and a correction method of signal measurement are provided. In the method, a transmitted signal and a received signal are divided into a plurality of transmitted signal groups and a plurality of received signal groups according to a time length, respectively. The received signal is related to a signal received after the transmitted signal is transmitted, and the transmitted signal is a periodic signal. A plurality of to-be-evaluated groups are selected from the received signal groups according to a correlation between the transmitted signal groups and the received signal groups. The correlation corresponds to a delay between the transmitted signal and the received signal. The signal energy of the received signal is determined according to the signal energy of the to-be-evaluated groups. Accordingly, the accuracy of signal measurement can be improved.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: May 18, 2021
    Assignee: Acer Incorporated
    Inventors: Po-Jen Tu, Jia-Ren Chang, Kai-Meng Tzeng
  • Patent number: 11011430
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Publication number: 20210143270
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first channel layer, a first barrier layer, a gate electrode and an insulating structure. The substrate has a recess, and the first channel layer, the first barrier layer, the gate electrode and the insulating structure are disposed in the recess. The first channel layer covers a surface of the recess. The first barrier layer is disposed on a surface of the first channel layer. A surface of a bottom portion of the first barrier layer is covered by the gate electrode, and a top surface of the gate electrode is lower than a topmost surface of the substrate. Surfaces of the gate electrode and a top portion of the first barrier layer are covered by the insulating structure.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Hao-Chuan Chang, Kai Jen
  • Patent number: 11004685
    Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Chen-En Yen, Chin Wei Kang, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii
  • Publication number: 20210134981
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.
    Type: Application
    Filed: December 2, 2019
    Publication date: May 6, 2021
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20210133971
    Abstract: A method of characterizing a serum or plasma portion of a specimen in a specimen container provides a fine-grained HILN index (hemolysis, icterus, lipemia, normal) of the serum or plasma portion of the specimen, wherein the H, I, and L classes may each have five to seven sub-classes. The HILN index may also have one un-centrifuged class. Pixel data of an input image of the specimen container may be processed by a deep semantic segmentation network having, in some embodiments, more than 100 layers. A small front-end container segmentation network may be used to determine a container type and boundary, which may additionally be input to the deep semantic segmentation network. A discriminative network may be used to train the deep semantic segmentation network to generate a homogeneously structured output. Quality check modules and testing apparatus configured to carry out the method are also described, as are other aspects.
    Type: Application
    Filed: June 10, 2019
    Publication date: May 6, 2021
    Applicant: Siemens Healthcare Diagnostics Inc.
    Inventors: Kai Ma, Yao-Jen Chang, Terrence Chen, Benjamin S. Pollack
  • Publication number: 20210134993
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 6, 2021
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: 10998320
    Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 4, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kai Jen, Shou-Te Wang
  • Patent number: 10998323
    Abstract: A dynamic random access memory (DRAM) including a substrate, transistors, bit line sets, conductive structures, and word line sets is provided. The transistors are arranged on the substrate in an array. Each transistor includes a first conductive layer, a second conductive layer, and a third conductive layer. The bit line sets are disposed in parallel along a Y direction and pass through the transistors. Each bit line set includes a first bit line and a second bit line electrically connected to the first conductive layer of each transistor respectively. The conductive structures are located in the transistors. The conductive structures are electrically connected to the second conductive layer of the transistors and the substrate. The word line sets are disposed in parallel along an X direction. Each word line set includes a first word line and a second word line located on sidewalls of each transistor respectively.
    Type: Grant
    Filed: August 4, 2019
    Date of Patent: May 4, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Kai Jen, Ting-Ting Ke
  • Patent number: 10968567
    Abstract: A method for preparing ?-cellulose, a spinning composition, and a fiber material are provided. The method for preparing ?-cellulose includes providing a coffee residue; subjecting the coffee residue to a decolorization treatment, obtaining a white powder; reacting the white powder with an alkaline solution, obtaining a mixture; filtering the mixture to produce a filter cake; and baking the filter cake to obtain ?-cellulose.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 6, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shi-Kuang Hwang, Tien-Ching Lu, Kai-Jen Hsiao, Jing-Wen Tang
  • Publication number: 20210013209
    Abstract: Provided is a DRAM including a substrate, first bit line structures, second bit line structures, and word line structures. The substrate has active regions each including pillar structures arranged along a first direction. Two first bit line structures extended along the first direction and buried in the substrate are disposed between the active regions arranged along a second direction. Each second bit line structure is located between the pillar structures and extended through the active regions along the second direction to be disposed on the first bit line structures and electrically connected to the first bit line structures. The word line structures are disposed on and spaced apart from the second bit line structures. Each word line structure extended along the second direction is located between the pillar structures and passes through the active regions arranged along the second direction. A manufacturing method of the DRAM is also provided.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 14, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Kai Jen, Hao-Chuan Chang