Abstract: A finger device including a finger segment, a finger base, a first steering control mechanism, a first actuator, a second steering control mechanism, a universal joint and a second actuator is provided. The finger base is connected to one end of the finger segment, and the first steering control mechanism is disposed on the finger base. The first actuator is configured to provide a first moment to the first steering control mechanism, so that the finger segment and the finger base have a degree of freedom in a first moving direction. The second steering control mechanism is disposed on the finger base. The second actuator is configured to provide a second moment to the universal joint. The universal joint is rotatably connected between the second actuator and the second steering control mechanism, so that the finger segment has a degree of freedom in a second moving direction.

Abstract: A finger device including a finger segment, a finger base, a first steering control mechanism, a first actuator, a second steering control mechanism, a universal joint and a second actuator is provided. The finger base is connected to one end of the finger segment, and the first steering control mechanism is disposed on the finger base. The first actuator is configured to provide a first moment to the first steering control mechanism, so that the finger segment and the finger base have a degree of freedom in a first moving direction. The second steering control mechanism is disposed on the finger base. The second actuator is configured to provide a second moment to the universal joint. The universal joint is rotatably connected between the second actuator and the second steering control mechanism, so that the finger segment has a degree of freedom in a second moving direction.

Abstract: A textile detection module is suitable for detecting a test specimen. The textile detection module includes a height sensor, an excitation light source, an optical detector, and a focuser. The height sensor is suitable for measuring a height of the test specimen to generate a height signal. The excitation light source provides an excitation light beam. The optical detector is disposed on a transmission path of the excitation light beam and is suitable for receiving the excitation light beam and emitting the excitation light beam along the optical axis and receiving a detection light beam to generate a detection result. The focuser is disposed on the transmission path of the excitation light beam emitted by the optical detector. The focuser includes a focus lens suitable for converting the excitation light beam into a focused excitation light beam.

Abstract: A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.

Abstract: A semiconductor structure and its manufacturing method are provided. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned cover curtain layer has an opening, and the opening includes a main body portion and two extension portions located at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the insulating layer. The first sacrificial layer fills the extension portions and defines a recess in the main body portion. The second sacrificial layer is formed in the recess defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer located in the extension portions.

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.

Abstract: A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.

Abstract: A semiconductor structure includes a semiconductor substrate, a gate stack disposed over the semiconductor substrate, a first oxide spacer disposed along a sidewall of the gate stack, a protection portion disposed over the first oxide spacer, and an interlayer dielectric layer disposed over the semiconductor substrate. The first oxide spacer and the protection portion are disposed between the gate stack and the interlayer dielectric layer.

Abstract: A multi-gate semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having an active area and an isolation structure adjacent to the active area. The semiconductor structure includes a gate structure formed on the substrate and a gate dielectric layer between the gate structure and the substrate. The gate structure includes a first part above the top surface of the substrate and a second part connected to the first part. The second part of the gate structure is formed in the isolation structure, wherein the isolation structure is in direct contact with the bottom surface and sidewalls of the second part of the gate structure. A method of manufacturing the semiconductor structure includes partially etching the isolation structure to form a trench exposing the top portion of sidewalls of the substrate. The gate dielectric layer and the gate structure extend into the trench.

Abstract: A muscle training system configured to train at least one target muscle of a human body includes a muscle training equipment and a controller. The muscle training equipment includes at least one resistance adjustment assembly and at least one vibration detector. The at least one resistance adjustment assembly is configured to provide a resistance force as a training load. The at least one vibration detector is configured to be disposed on the at least one target muscle and produces at least one muscle vibration signal based on an activity of the at least one target muscle training under the resistance force. The controller is configured to control the at least one resistance adjustment assembly to adjust the resistance force according to the at least one muscle vibration signal.

Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having a trench. The semiconductor structure also includes an oxide layer conformally formed in the trench and a protective layer formed in the trench. Also, the protective layer is conformally formed on the oxide layer. The semiconductor structure further includes an insulating material layer in the trench, and the insulating material layer is formed above the protective layer, wherein a top surface of the insulating material layer is higher than a top surface of the protective layer.

Abstract: A conductive fiber and a method for fabricating the conductive fiber are provided. The method for fabricating the conductive fiber includes the following steps. A first solution is provided, where the first solution includes a spinnable polymer dissolved in a first solvent, wherein the weight ratio of the spinnable polymer to the first solvent is from 5:95 to 20:80. A second solution is provided, wherein the second solution includes a conductive material dispersed in a second solvent, and the weight ratio of the conductive material to the second solvent is from 5:95 to 20:80. The shape of the conductive material is dendritic or snowflake-like. Next, a wet spinning process employing the first solution and the second solution is performed to obtain the conductive fiber.

Abstract: A method of forming a solderable solder deposit on a contact pad, comprising the steps of providing an organic, non-conductive substrate which exposes said contact pad under an opening of a first non-conductive resist layer, depositing a conductive layer inside and outside the opening such that an activated surface results, thereby forming an activated opening, electrolytically depositing nickel or nickel alloy into the activated opening such that nickel/nickel alloy is deposited onto the activated surface, electrolytically depositing tin or tin alloy onto the nickel/nickel alloy, with the proviso that the electrolytic deposition of later steps results in an entirely filled activated opening, wherein the entirely filled activated opening is completely filled with said nickel/nickel alloy, or in the entirely filled activated opening the total volume of nickel/nickel alloy is higher than the total volume of tin and tin alloy, based on the total volume of the entirely filled activated opening.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first channel layer, a first barrier layer, a gate electrode and an insulating structure. The substrate has a recess, and the first channel layer, the first barrier layer, the gate electrode and the insulating structure are disposed in the recess. The first channel layer covers a surface of the recess. The first barrier layer is disposed on a surface of the first channel layer. A surface of a bottom portion of the first barrier layer is covered by the gate electrode, and a top surface of the gate electrode is lower than a topmost surface of the substrate. Surfaces of the gate electrode and a top portion of the first barrier layer are covered by the insulating structure.

Abstract: A dynamic random access memory (DRAM) including a substrate, transistors, bit line sets, conductive structures, and word line sets is provided. The transistors are arranged on the substrate in an array. Each transistor includes a first conductive layer, a second conductive layer, and a third conductive layer. The bit line sets are disposed in parallel along a Y direction and pass through the transistors. Each bit line set includes a first bit line and a second bit line electrically connected to the first conductive layer of each transistor respectively. The conductive structures are located in the transistors. The conductive structures are electrically connected to the second conductive layer of the transistors and the substrate. The word line sets are disposed in parallel along an X direction. Each word line set includes a first word line and a second word line located on sidewalls of each transistor respectively.

Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.

Abstract: A method for preparing ?-cellulose, a spinning composition, and a fiber material are provided. The method for preparing ?-cellulose includes providing a coffee residue; subjecting the coffee residue to a decolorization treatment, obtaining a white powder; reacting the white powder with an alkaline solution, obtaining a mixture; filtering the mixture to produce a filter cake; and baking the filter cake to obtain ?-cellulose.