Abstract: A radar detection system and a radar field of view (FOV) direction adjustment method are provided. A processing unit of the radar detection system performs the following steps in one scanning round: obtaining at least one cluster of a current frame and a current status and a next status of each cluster based on digital feedback signals; and determining a displacement, determining, based on the current status of a tracked cluster in the at least one cluster and the displacement, whether the tracked cluster is located on an edge of a current FOV of a radar unit, and sending a control signal based on the next status of the tracked cluster in response to the tracked cluster being located on the edge of the current FOV, to adjust an FOV direction of the radar unit.

Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.

Abstract: A portable electric fan is provided and includes a shell, a fan module, and a plurality of combined seat groups. The shell has a first surface, a second surface opposite to the first surface, and a surrounding side surface that is connected to the first surface and the second surface. The shell has a hollow portion. The fan module is mounted in the hollow portion. The combined seat groups are mounted on the surrounding side surface, and each of the combined seat groups includes two bases and a bracket detachably mounted to the two bases. Each of the two bases has a first through hole and a second through hole, and an extending length direction of the first through hole and an extending direction of the second through hole are staggered relative to the surrounding side surface.

Abstract: A ceiling fan and a surrounding device thereof are provided. The ceiling fan includes a main body, a bracket set connected to the main body, and a surrounding device connected to the bracket set. The main body includes a main shaft, a motor, and a plurality of ceiling fan blades. The bracket set includes a plurality of brackets, and each of the brackets has one end connected to the main shaft. The surrounding device is connected to another end of each of the brackets that is relatively far away from the main shaft, and the surrounding device is roundly arranged around and spaced apart from an end of each of the ceiling fan blades that is relatively far away from the motor. The surrounding device includes at least one functional component that is configured to disinfect or sterilize air or to provide lighting.

Abstract: A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.

Abstract: A non-contact exercise vital sign detection method is provided. At least one candidate position having an energy intensity exceeding an energy threshold is pre-selected from a vibration frequency map, and a position having a vibration frequency meeting a vital sign parameter range is then selected as a target position from the at least one candidate position. Accordingly, phase data obtained according to the target position facilitates accurate detection of a vital sign parameter of a subject.

Abstract: A data pre-processing method is provided. By using an energy distribution parameter set obtained through beamforming scanning, a signal-to-noise ratio of a signal can be improved and a detection range region can be automatically generated, thereby improving an object tracking effect. An exercise vital sign detection radar is also provided.

Abstract: A ceiling fan and a surrounding device thereof are provided. The ceiling fan includes a main body, a bracket set connected to the main body, and a surrounding device connected to the bracket set. The main body includes a main shaft, a motor, and a plurality of ceiling fan blades. The bracket set includes a plurality of brackets, and each of the brackets has one end connected to the main shaft. The surrounding device is connected to another end of each of the brackets that is relatively far away from the main shaft, and the surrounding device is roundly arranged around and spaced apart from an end of each of the ceiling fan blades that is relatively far away from the motor. The surrounding device includes at least one functional component that is configured to disinfect or sterilize air or to provide lighting.

Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.

Abstract: A ceiling fan blade is provided. The ceiling fan blade is configured to be mounted on a rotating base, and includes a main body and a blade holder connected to the main body. The blade holder is configured to be mounted on the rotating base. The main body includes a windward part arranged adjacent to a side of the main body and a plurality of air guiding structures arranged adjacent to the windward part. Each of the air guiding structures and the side of the main body that is adjacent to the windward part is 0.2 to 0.4 times of a width of the main body.

Abstract: A ceiling fan blade is provided. The ceiling fan blade is configured to be mounted on a rotating base, and includes a main body and a blade holder connected to the main body. The blade holder is configured to be mounted on the rotating base. The main body includes a windward part arranged adjacent to a side of the main body and a plurality of air guiding structures arranged adjacent to the windward part. Each of the air guiding structures and the side of the main body that is adjacent to the windward part is 0.2 to 0.4 times of a width of the main body.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.

Abstract: A ceiling fan light kit and a ceiling fan connecting module are provided. The ceiling fan light kit includes the ceiling fan connecting module, a light board, and a light cover module. The ceiling fan connecting module includes a mounting plate and a base. The mounting plate has a plurality of arc holes, a plurality of rotary fixing structures, and a plurality of backstop structures, and a placing hole and a fixing hole are respectively formed at two ends of each of the arc holes. The mounting plate has one of the rotary fixing structures and one of the backstop structures that are spaced apart from one another formed at two sides of each of the arc holes. The base has a bottom plate, a cooling portion, and a plurality of dowels that are respectively disposed in the placing holes.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

Abstract: A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.

Abstract: The present invention refers to a method of preparing a high density interconnect printed circuit board (HDI PCB) including microvias filled with copper comprising the steps of: a1) providing a multi-layer substrate comprising (i) a stack assembly of an electrically conductive interlayer embedded between two insulating layers, (ii) a cover layer, and (iii) a microvia extending from the peripheral surface and ending on the conductive interlayer; b1) depositing a conductive layer; or a2) providing a multi-layer substrate comprising (i) a stack assembly of an electrically conductive interlayer embedded between two insulating layers, (ii) a microvia extending from the peripheral surface and ending on the conductive interlayer; b2) depositing a conductive layer; and c) electrodepositing a copper filling in the microvia and a first copper layer on the conductive layer which form together a planar surface and the thickness of the first copper layer is from 0.1 to 3 ?m.

Abstract: A method for processing digital signals is provided. In the method, a plurality of digital signals corresponding to radar signals received by a receiving terminal are superposed, so as to reduce noise caused by environmental interference. Therefore, according to an output signal obtained after the superposition, accurate characterization information of a to-be-detected object can be obtained.

Abstract: Provided is a DRAM including a substrate, first bit line structures, second bit line structures, and word line structures. The substrate has active regions each including pillar structures arranged along a first direction. Two first bit line structures extended along the first direction and buried in the substrate are disposed between the active regions arranged along a second direction. Each second bit line structure is located between the pillar structures and extended through the active regions along the second direction to be disposed on the first bit line structures and electrically connected to the first bit line structures. The word line structures are disposed on and spaced apart from the second bit line structures. Each word line structure extended along the second direction is located between the pillar structures and passes through the active regions arranged along the second direction. A manufacturing method of the DRAM is also provided.

Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first channel layer, a first barrier layer, a gate electrode and an insulating structure. The substrate has a recess, and the first channel layer, the first barrier layer, the gate electrode and the insulating structure are disposed in the recess. The first channel layer covers a surface of the recess. The first barrier layer is disposed on a surface of the first channel layer. A surface of a bottom portion of the first barrier layer is covered by the gate electrode, and a top surface of the gate electrode is lower than a topmost surface of the substrate. Surfaces of the gate electrode and a top portion of the first barrier layer are covered by the insulating structure.