Patents by Inventor Kai Shen

Kai Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088497
    Abstract: A battery for a mobile device includes: a battery housing including an inner wall, an opposing outer wall, a rear wall, and an opposing forward wall, the rear and forward walls each joining the inner and outer walls; an electrical contact disposed on the inner wall, configured to engage with an electrical interface within a device housing; a seal on the inner wall surrounding the electrical contact and a further portion of the inner wall, and configured to engage a complementary surface within the device housing; a hook extending from the forward wall, configured to engage the device housing to establish a pivot axis of the battery housing during battery insertion and removal; and a latch extending from the rear wall, biased towards an extended position to secure the battery within the device housing, and movable to a retracted position to release the battery from the device housing.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Andrew Ellis, Xinghua Shi, Mu-Kai Shen
  • Patent number: 11887012
    Abstract: A computing device identifies an anomaly among a plurality of observation vectors. An observation vector is projected using a predefined orthogonal complement matrix. The predefined orthogonal complement matrix is determined from a decomposition of a low-rank matrix. The low-rank matrix is computed using a robust principal component analysis algorithm. The projected observation vector is multiplied by a predefined demixing matrix to define a demixed observation vector. The predefined demixing matrix is computed using an independent component analysis algorithm and the predefined orthogonal complement matrix. A detection statistic value is computed from the defined, demixed observation vector. When the computed detection statistic value is greater than or equal to a predefined anomaly threshold value, an indicator is output that the observation vector is an anomaly.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: January 30, 2024
    Assignee: SAS Institute Inc.
    Inventors: Sudipta Kolay, Steven Guanxing Xu, Kai Shen, Zohreh Asgharzadeh Talebi
  • Patent number: 11881690
    Abstract: Provided is an insulating coating device for an electric wire, including a pressing pipe. The pressing pipe includes two first pressing parts which are configured to divide the pressing pipe into two parts along a longitudinal cross section of the pressing pipe, an inner wall of the pressing pipe is provided with an air bag, and the air bag is provided with an air pipe joint which penetrates to an outside of the pressing pipe. In the insulating coating device for the electric wire, a self-curing insulating material is coated on joints of the electric wires, the air bag is used to squeeze the self-curing insulating material such that the self-curing insulating material is shaped and compacted, so that cavities generated in a coating process is reduced, and the self-curing insulating material is uniformly attached to the joints of the electric wires.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: January 23, 2024
    Assignee: STATE GRID HUZHOU POWER SUPPLY COMPANY
    Inventors: Zhen Chen, Jing Xu, Wenhui Xu, Weixun Qin, Yongsheng Xu, Zhen Wang, Liupei Wei, Feng Zhou, Xinlong Wu, Xiaobin Shen, Jie Chai, Meng Tang, Kai Shen
  • Patent number: 11851318
    Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chuan Teng, Ching-Kai Shen, Jung-Kuo Tu, Wei-Cheng Shen, Xin-Hua Huang, Wei-Chu Lin
  • Publication number: 20230399226
    Abstract: The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Fan Hu, Wen-Chuan Tai, Li-Chun Peng, Hsiang-Fu Chen, Ching-Kai Shen, Hung-Wei Liang, Jung-Kuo Tu
  • Publication number: 20230382718
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first substrate having a top surface is received. A semiconductor layer is formed over the first substrate. A cavity is formed at the top surface of the semiconductor layer. A second substrate is bonded over the first substrate to cover the semiconductor layer. The second substrate has a through hole connected to the cavity of the semiconductor layer. A eutectic sealing structure is formed on the second substrate to cover the through hole. The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: YI-CHUAN TENG, CHING-KAI SHEN, JUNG-KUO TU
  • Publication number: 20230382719
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
  • Patent number: 11824215
    Abstract: A battery for a mobile device includes: a battery housing including an inner wall, an opposing outer wall, a rear wall, and an opposing forward wall, the rear and forward walls each joining the inner and outer walls; an electrical contact disposed on the inner wall, configured to engage with an electrical interface within a device housing; a seal on the inner wall surrounding the electrical contact and a further portion of the inner wall, and configured to engage a complementary surface within the device housing; a hook extending from the forward wall, configured to engage the device housing to establish a pivot axis of the battery housing during battery insertion and removal; and a latch extending from the rear wall, biased towards an extended position to secure the battery within the device housing, and movable to a retracted position to release the battery from the device housing.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 21, 2023
    Assignee: Zebra Technologies Corporation
    Inventors: Andrew Ellis, Xinghua Shi, Mu-Kai Shen
  • Patent number: 11822204
    Abstract: An electronic paper package structure, including a substrate, an electronic ink layer, a cover plate, a water vapor barrier film and an adhesive layer, is provided. The electronic ink layer is disposed on the substrate. The cover plate covers the electronic ink layer. The water vapor barrier film covers the substrate and the electronic ink layer. The adhesive layer is directly bonded between the cover plate and the water vapor barrier film to seal the substrate and the electronic ink layer. The adhesive layer is not bonded between the cover plate and the electronic ink layer.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: November 21, 2023
    Assignee: E INK HOLDINGS INC.
    Inventors: Jen-Shiun Huang, Huang-Kai Shen, Ko-Fan Tu
  • Patent number: 11807520
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Chuan Teng, Ching-Kai Shen, Jung-Kuo Tu
  • Patent number: 11772960
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
  • Publication number: 20230187950
    Abstract: An adapter for a charging cradle includes: a perimeter wall defining a channel between first and second ends; a first device interface on an inner surface of the perimeter wall in communication with the first end, the first device interface configured to receive and align a first mobile device configuration with the charging cradle; a second device interface on the inner surface of the perimeter wall in communication with the second end, the second device interface configured to receive and align a second mobile device configuration with the charging cradle; a cradle interface on an outer surface of the perimeter wall, and configured to couple the adapter to the charging cradle in one of (i) a first orientation to expose a connector of the charging cradle via the first end of the channel, and (ii) a second orientation to expose the connector via the second end of the channel.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: Mu-Kai Shen, Liao-Hsun Chen, Chao Yu Chang
  • Patent number: 11586234
    Abstract: The application discloses a power supply circuit and a power supply device. A drain of a first N-type metal-oxide-semiconductor field-effect transistor (MOSFET) receives a first input voltage. A filter is coupled to a source of the first N-type MOSFET and is configured to output an output voltage. A non-inverting input terminal of an operational amplifier is coupled to a ground terminal through a first capacitor. A control circuit is coupled to an inverting input terminal of the operational amplifier. One terminal of a switch is coupled to a gate of the first N-type MOSFET, and the other terminal is switchably coupled to the control circuit or an output terminal of the operational amplifier, so that the gate of the first N-type MOSFET is switched to be coupled to the control circuit or the output terminal of the operational amplifier.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 21, 2023
    Assignee: PEGATRON CORPORATION
    Inventors: Hsiao-Wei Sung, Chun-Wei Ko, Yu-Kai Shen, Chih-Wei Huang
  • Publication number: 20230021112
    Abstract: A display device, including a flexible substrate, multiple lighting units, and multiple signal lines, is provided. The lighting units and the signal lines are located on the flexible substrate, and the signal lines are respectively electrically connected to the lighting units. Each signal line includes multiple first conductive patterns, at least one second conductive pattern, and at least one third conductive pattern. The first conductive patterns are located on the flexible substrate. The second conductive pattern is located on the first conductive patterns, and two ends of each second conductive pattern are respectively connected to two first conductive patterns. In a stretched state, the two first conductive patterns twist the commonly connected second conductive pattern. The third conductive pattern is superimposed on the second conductive pattern.
    Type: Application
    Filed: October 29, 2021
    Publication date: January 19, 2023
    Applicant: Au Optronics Corporation
    Inventors: Zih-Shuo Huang, Tsung-Ying Ke, Shang-Kai Shen
  • Publication number: 20220411260
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: YI-CHUAN TENG, CHING-KAI SHEN, JUNG-KUO TU
  • Patent number: D978862
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 21, 2023
    Assignee: Zebra Technologies Corporation
    Inventors: Mu-Kai Shen, Hui-Chi Kuo, Chandra M. Nair
  • Patent number: D995529
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: August 15, 2023
    Assignee: Zebra Technologies Corporation
    Inventors: Carl DeGiovine, Robert K. Liao, JaeHo Choi, Sunghun Lim, Chandra M. Nair, Jason H. Legoff, Mu-Kai Shen
  • Patent number: D998617
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 12, 2023
    Assignee: Symbol Technologies, LLC
    Inventors: Mu-Kai Shen, Huang Chih Huang, Michael A. Charpin
  • Patent number: D1001093
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 10, 2023
    Assignee: Zebra Technologies Corporation
    Inventors: Sunghun Lim, Hui-Chi Kuo, Dae Suk Noh, Mu-Kai Shen
  • Patent number: D1012935
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: January 30, 2024
    Assignee: Zebra Technologies Corporation
    Inventors: Mu-Kai Shen, Huang Chih Huang, Chandra M. Nair, Mark Thomas Fountain