Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.

Abstract: An oscillator layout includes: a first row layout region constituted by sequentially arranging a second B layout region, second A layout region, third B layout region and third A layout region in parallel; and a second row layout region constituted by sequentially arranging a first A layout region, first B layout region, fourth A layout region and fourth B layout region in parallel. Inputs and outputs of the first A layout region, second A layout region, third A layout region and fourth A layout region constitute a first ring topology, inputs and outputs of the first B layout region and third B layout region constitute a second ring topology, inputs and outputs of the second B layout region and fourth B layout region constitute a third ring topology, the second ring topology and third ring topology are both electrically connected to the first ring topology.

Abstract: Provided are a resistance calibration circuit, a resistance calibration method, and a memory. When a short calibration enable signal is valid, calibration processing is performed on a resistance control code in one of a short calibration mode and a full calibration mode based on a comparison result of a last latched value and an initial default value of the resistance control code.

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Abstract: An electrostatic protection circuit includes: a monitoring unit, a discharge unit, and a controllable voltage dividing unit, where the monitoring unit is connected to at least one probe pad, a discharge unit and a controllable voltage dividing unit, and the monitoring unit is configured to generate a first trigger signal in response to that an electrostatic pulse is present on any probe pad; the discharge unit connected between the at least one probe pad and the ground pad, and configured to form, under control of the first trigger signal, at least one path for discharging electrostatic charges to the ground pad; and the controllable voltage dividing unit is connected to the discharge unit and is configured to share a part of voltage of the first trigger signal for the discharge unit.

Abstract: A gimbal module includes a first carrier including a receiving chamber, a first bracket accommodated in the receiving chamber, a lens assembly fixed to the first bracket, and a flexible circuit board connected to the lens assembly. The flexible circuit board extends in an S-shape on a plane as viewed in a height direction of the gimbal module. An electronic device including the gimbal module is also disclosed.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a discharge transistor, located between the power supply pad and a ground pad, and configured to be turned on under a control of the trigger signal, so as to discharge an electrostatic charge to the ground pad; and a first controllable voltage division unit, connected to the discharge transistor, and configured to switch an operating mode under a control of a control signal. The operating mode includes a voltage division mode. When operating in the voltage division mode, the controllable voltage division unit is configured to carry a part of a voltage applied by the electrostatic charge to the discharge transistor.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.

Abstract: An objective of the disclosure is to provide a power supply cell of a power supply system and a power supply system using the same.

Abstract: A calibration control circuit includes an off-chip calibration circuit, an on-chip calibration circuit and a mode switching circuit. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a user. The on-chip calibration circuit is configured to receive an enable signal and perform a ZQ self-calibration process on the memory to obtain a second calibration code adapted to a current environmental parameter when the enable signal is in an active state. The mode switching circuit is configured to receive a calibration mode signal, the first calibration code and the second calibration code, and determine the first calibration code as a ZQ calibration code when the calibration mode signal indicates an off-chip calibration mode, or, determine the second calibration code as the ZQ calibration code when the calibration mode signal indicates an on-chip calibration mode.

Abstract: A method comprises providing first and second end systems sharing the same A619 origin and destination codes, wherein the first end system has a first A618 label/sublabel, and the second end system has a second A618 label/sublabel different from the first label/sublabel. When an uplink message is an A618 uplink with the first label/sublabel, the method sends an A619 uplink with A619 destination code via a first end system port. If an uplink message is an A618 uplink with the second label/sublabel, the method sends an A619 uplink with A619 destination code via a second end system port. When downlink message is received with the A619 origin code on the first end system port, the method sends an A618 downlink with the first label/sublabel. If downlink message is received with the A619 origin code on the second end system port, the method sends an A618 downlink with the second label/sublabel.

Abstract: A power supply cell of a power supply system including a first power conversion circuit to output a first DC voltage, a second power conversion circuit to output a second DC voltage, a first controllable unidirectional semiconductor switch to generate a first conduction path from the first power conversion circuit to the second power conversion circuit, a first unidirectional semiconductor switch to generate a second conduction path from the first power conversion circuit to the second power conversion circuit, a second unidirectional semiconductor switch to generate a third conduction path from the first power conversion circuit to the second power conversion circuit, a first low-pass filter, and a controlling unit operative to issue turn-on signal or turn-off signal to the first controllable unidirectional semiconductor switch to supply current to the low-pass filter via the first conduction path or both of the second conduction path and the third conduction path.

Abstract: The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.

Abstract: A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.

Abstract: A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

Abstract: Provided are an Electro Static Discharge (ESD) circuit and a memory. The ESD circuit includes: a detection circuit and multiple electrostatic discharge circuits. The detection circuit includes at least one sub-detection circuit connected between a first power end and a second power end. Each sub-detection circuit generates a sub-trigger signal based on a voltage change between the first power end and the second power end. The multiple electrostatic discharge circuits are connected between the first power end and the second power end. The multiple electrostatic discharge circuits are configured to be turned on according to the one or more sub-trigger signals.

Abstract: A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes a master chip and a plurality of slave chips. The master chip and the slave chips are each provided with a first transmission terminal and a second transmission terminal, where the first transmission terminals are connected to each other, and the second transmission terminals are connected to each other; and a first signal receiver and an address transmitter are provided in the master chip, and a second signal receiver is provided in the slave chip, the address transmitter is configured to send an address signal; a current slave chip sends the ZQ flag signal after completing the calibration; and the address transmitter is configured to send a next address signal.