Abstract: The present disclosure provides a voltage reference source circuit for generating a reference voltage, the voltage reference source circuit comprises a starting circuit, a current generating circuit, and an output voltage reference circuit electrically connected in sequence. The starting circuit provides a starting voltage for the voltage reference source circuit to prevent the voltage reference source circuit from operating in zero state area. The current generating circuit generates a working current for the output voltage reference circuit; and the output voltage reference circuit is used to realize the reference voltage output with zero temperature coefficient according to the working current output by the current generating circuit. A low power consumption power supply system is also disclosed.

Abstract: The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.

Abstract: A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.

Abstract: A display panel and a display device are disclosed, relating to the display technical field. The display panel comprises a display layer and a light control layer which are laminated, the light control layer comprises a plurality of light control pixel areas, the light control pixel areas comprise a thin film transistor, the display layer comprises a plurality of display pixel areas, and the display pixel areas comprise a green sub-pixel; the orthographic projection of the green sub-pixel on the light control pixel area is close to the area where the thin film transistor is located.

Abstract: A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

Abstract: An anaerobic-AO-SACR combined advanced nitrogen removal system for high ammonia-nitrogen wastewater, in which high ammonia-nitrogen wastewater first enters an anaerobic reactor to remove most of organic matters from the wastewater, effluent water enters an AO reactor for nitrogen removal by pre-denitrification in an anoxic zone and for removal of the remaining organic matters and nitrification of ammonia nitrogen in an aerobic zone, and then the effluent water enters an intermediate pool. Meanwhile, under the control of a water quality testing device and a PLC controller, a part of raw water is introduced into the intermediate pool to adjust the carbon nitrogen ratio of the wastewater.

Abstract: Provided are an Electro Static Discharge (ESD) circuit and a memory. The ESD circuit includes: a detection circuit and multiple electrostatic discharge circuits. The detection circuit includes at least one sub-detection circuit connected between a first power end and a second power end. Each sub-detection circuit generates a sub-trigger signal based on a voltage change between the first power end and the second power end. The multiple electrostatic discharge circuits are connected between the first power end and the second power end. The multiple electrostatic discharge circuits are configured to be turned on according to the one or more sub-trigger signals.

Abstract: A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes a master chip and a plurality of slave chips. The master chip and the slave chips are each provided with a first transmission terminal and a second transmission terminal, where the first transmission terminals are connected to each other, and the second transmission terminals are connected to each other; and a first signal receiver and an address transmitter are provided in the master chip, and a second signal receiver is provided in the slave chip, the address transmitter is configured to send an address signal; a current slave chip sends the ZQ flag signal after completing the calibration; and the address transmitter is configured to send a next address signal.

Abstract: A memory device includes: two calibration resistor interfaces connected to the same ZQ calibration resistor; and a first master chip, first slave chips, a second master chip, and second slave chips, which are commonly connected to the ZQ calibration resistor; in a command mode, a first signal receiver is used to receive a ZQ calibration command, a second signal receiver is used to receive and delay the ZQ calibration command, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and after the calibration is completed, the first slave chips and the second slave chips send a ZQ flag signal through second transmission terminals.

Abstract: Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.

Abstract: A package structure includes N first pads, N redistribution layers, second pads and third pads. Each first pad is formed by a interconnect layer exposed by one via hole. Each redistribution layer covers the isolation layer and is electrically connected with a corresponding first pad. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The exposed parts of each redistribution layer form a second and a third pad. Both an offset direction and an offset distance between a center point of the second pad and that of a corresponding first pad are same. A relative position between the second pad and the third pad for some redistribution layers is different from that for others.

Abstract: A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.

Abstract: A circuit for calibration control includes an off-chip calibration circuit and a mode switching circuit, and the off-chip calibration circuit includes a preprocessing circuit and a mapping circuit. The preprocessing circuit is configured to receive a current set of environmental parameters, decode the current set of environmental parameters and output parameter decoding signals. The mapping circuit is configured to receive the parameter decoding signals and output a first calibration code according to the parameter decoding signals. The mode switching circuit is configured to receive a calibration mode signal and the first calibration code, and determine the first calibration code as a ZQ calibration code in a case where the calibration mode signal indicates an off-chip calibration mode.

Abstract: A method and apparatus for processing an action of a virtual object, and a storage medium are provided. The method specifically includes: receiving an action instruction, the action instruction including: an action identifier and time-dependent information of performing an action associated with the action identifier; determining an action video frame sequence corresponding to the action identifier; determining, from the action video frame sequence, an action state image corresponding to a preset state image of the virtual object at a target time, the target time being determined according to the time-dependent information; generating a connection video frame sequence according to the action state image, the connection video frame sequence connecting the preset state image with the action video frame sequence; and splicing the connection video frame sequence with the action video frame sequence, to obtain an action video.

Abstract: A calibration control circuit includes an off-chip calibration circuit, an on-chip calibration circuit and a mode switching circuit. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a user. The on-chip calibration circuit is configured to receive an enable signal and perform a ZQ self-calibration process on the memory to obtain a second calibration code adapted to a current environmental parameter when the enable signal is in an active state. The mode switching circuit is configured to receive a calibration mode signal, the first calibration code and the second calibration code, and determine the first calibration code as a ZQ calibration code when the calibration mode signal indicates an off-chip calibration mode, or, determine the second calibration code as the ZQ calibration code when the calibration mode signal indicates an on-chip calibration mode.

Abstract: A circuit for controlling calibration includes a process circuit, an off-chip calibration circuit and a mode switching circuit. The process circuit is configured to perform, in a first test mode, a process corner test on the memory to obtain a test result signal, the test result signal being used for determining a process corner parameter. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a controller, the first calibration code being determined by the controller according to a current environment parameter of the memory and the process corner parameter.

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Abstract: The present disclosure relates to methods of writing data in nucleic acid chains and methods of reading data written in nucleic acid chains. The present disclosure also relates to a kit for writing and reading data in nucleic acid chains.