Patents by Inventor Kai Tian
Kai Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11303196Abstract: An objective of the present application is to provide an apparatus for conversion between AC power and DC power. The apparatus includes a first power conversion circuit having a first AC side and a first DC side, at least one second power conversion circuit each having a second AC side and a second DC side; and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit.Type: GrantFiled: March 25, 2021Date of Patent: April 12, 2022Assignee: ABB SCHWEIZ AGInventors: Kai Tian, Tinho Li, Kuenfaat Yuen, Mei Liang
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Patent number: 11295804Abstract: The present invention provides an output circuit and a chip. The output circuit includes a first-stage circuit, a second-stage circuit, a third-stage circuit, and a fourth-stage circuit. The first-stage circuit is configured to read serial data in a memory and divide the serial data into first voltage signals each at a specified rate level; the second-stage circuit is configured to receive the first voltage signals, generate a plurality of second voltage signals; the third-stage circuit is configured to: allocate a transmission path to each of the second voltage signals according to a ZQ calibration signal; and the fourth-stage circuit includes a pull-up circuit and a pull-down circuit, each including thin-gate low-threshold NMOS transistors, and the fourth-stage circuit is configured to generate output voltage signals of the output circuit. By eliminating the limit on a minimum operating power supply voltage, different high-speed data output ports are compatible, thereby improving efficiency.Type: GrantFiled: February 10, 2021Date of Patent: April 5, 2022Assignee: Changxin Memory Technologies, Inc.Inventor: Kai Tian
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Publication number: 20220103085Abstract: Voltage converter circuits including a first and second branch. The first branch is coupled between a first DC terminal and a second DC terminal and includes a first and second winding around a magnetic core. The first and second winding are coupled to an AC terminal via a common node. The second branch is coupled in parallel to the first branch between the first and second DC terminals and includes a third winding around the magnetic core. The third winding is coupled to the AC terminal such that the first and second branches convert a first voltage into a second voltage. The first, second and third windings are configured to cause magnetic flux generated by a differential mode (DM) component of a first current in the first branch and magnetic flux generated by the DM component of a second current in the second branch to enhance with each other.Type: ApplicationFiled: June 12, 2019Publication date: March 31, 2022Applicant: ABB Schweiz AGInventors: Kai Tian, Tinho Li, Kuenfaat Yuen, Mei Liang
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Publication number: 20220059137Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.Type: ApplicationFiled: August 18, 2021Publication date: February 24, 2022Inventors: Weibing SHANG, Fengqin ZHANG, Kangling JI, Kai TIAN, Xianjun WU
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Patent number: 11251862Abstract: In one embodiment, a method is provided. The method includes selecting, with a communications management system, a first satellite communications (SATCOM) system of a plurality of SATCOM systems as a primary SATCOM system based on user input, received by a human machine interface, that identifies the first SATCOM system as a user-selected SATCOM system. The method further includes automatically switching, with the communications management system, the primary SATCOM system from the first SATCOM system to a second SATCOM system of the plurality of SATCOM systems in response to: a fault status for the first SATCOM system; a loss of channel availability for the first SATCOM system; and/or a failed datalink message transmission for the first SATCOM system. The method further includes establishing a communication link between the primary SATCOM system and a ground station.Type: GrantFiled: July 14, 2020Date of Patent: February 15, 2022Assignee: Honeywell International Inc.Inventors: Zhenning Zhou, Zhijian Xu, Pi-Shien Liu, Kai Tian, Minghui Chen, Mei Tian
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Publication number: 20220021443Abstract: In one embodiment, a method is provided. The method includes selecting, with a communications management system, a first satellite communications (SATCOM) system of a plurality of SATCOM systems as a primary SATCOM system based on user input, received by a human machine interface, that identifies the first SATCOM system as a user-selected SATCOM system. The method further includes automatically switching, with the communications management system, the primary SATCOM system from the first SATCOM system to a second SATCOM system of the plurality of SATCOM systems in response to: a fault status for the first SATCOM system; a loss of channel availability for the first SATCOM system; and/or a failed datalink message transmission for the first SATCOM system. The method further includes establishing a communication link between the primary SATCOM system and a ground station.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Applicant: Honeywell International Inc.Inventors: Zhenning Zhou, Zhijian Xu, Pi-Shien Liu, Kai Tian, Minghui Chen, Mei Tian
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Publication number: 20210375328Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.Type: ApplicationFiled: December 11, 2019Publication date: December 2, 2021Inventors: KangLing JI, Hongwen LI, Kai TIAN
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Patent number: 11171557Abstract: A power converter includes a full-bridge conversion circuit. The full-bridge conversion circuit includes a first leg and a second leg. The first leg includes at least two switches coupled to each other at a first node, and the second leg includes at least two switches coupled to each other at a second node. The power converter further includes an AC filter. The AC filter includes a first inductor, a second inductor and a capacitor. The first inductor includes a first end coupled to the first node and a second end could be couple to a grid. The second inductor includes a first end coupled to the second node and a second end could be couple to the grid. The capacitor includes a first end coupled to the second end of the first inductor and a second end coupled to the second leg. The first end of the capacitor is electrically coupled to the second end of the first inductor during a cycle of an AC voltage of the grid.Type: GrantFiled: September 18, 2020Date of Patent: November 9, 2021Assignee: ABB Schweiz AGInventors: Sheng Zong, Guoxing Fan, Kai Tian, Mei Liang
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Patent number: 11164849Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.Type: GrantFiled: March 9, 2021Date of Patent: November 2, 2021Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Kai Tian, Hongwen Li
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Publication number: 20210273552Abstract: It is therefore an objective of the invention to provide an apparatus for conversion between AC power and DC power. The apparatus includes a first power conversion circuit having a first AC side and a first DC side, at least one second power conversion circuit each having a second AC side and a second DC side; and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit.Type: ApplicationFiled: March 25, 2021Publication date: September 2, 2021Inventors: Kai Tian, Tinho Li, Kuenfaat Yuen, Mei Liang
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Publication number: 20210265316Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.Type: ApplicationFiled: March 9, 2021Publication date: August 26, 2021Inventors: Kai TIAN, Hongwen LI
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Publication number: 20210211037Abstract: An apparatus for conversion between AC power and DC power. The apparatus includes: a first power conversion circuit having a first AC side and a DC side, at least one second power conversion circuit each having a second AC side and sharing the DC side with the first power conversion circuit, and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein: the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit.Type: ApplicationFiled: March 25, 2021Publication date: July 8, 2021Inventors: Kai Tian, Tinho Li, Kuenfaat Yuen, Mei Liang
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Publication number: 20210211050Abstract: An objective of the present application is to to provide a power supply cell of a power supply system and a power supply system using the same.Type: ApplicationFiled: March 25, 2021Publication date: July 8, 2021Inventors: Kuenfaat Yuen, Tinho Li, Kai Tian
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Publication number: 20210211051Abstract: An objective of the disclosure is to provide a power supply cell of a power supply system and a power supply system using the same.Type: ApplicationFiled: March 25, 2021Publication date: July 8, 2021Inventors: Kuenfaat Yuen, Tinho Li, Kai Tian
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Publication number: 20210193216Abstract: The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode.Type: ApplicationFiled: February 9, 2021Publication date: June 24, 2021Inventor: Kai TIAN
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Publication number: 20210166748Abstract: The present invention provides an output circuit and a chip. The output circuit includes a first-stage circuit, a second-stage circuit, a third-stage circuit, and a fourth-stage circuit. The first-stage circuit is configured to read serial data in a memory and divide the serial data into first voltage signals each at a specified rate level; the second-stage circuit is configured to receive the first voltage signals, generate a plurality of second voltage signals; the third-stage circuit is configured to: allocate a transmission path to each of the second voltage signals according to a ZQ calibration signal; and the fourth-stage circuit includes a pull-up circuit and a pull-down circuit, each including thin-gate low-threshold NMOS transistors, and the fourth-stage circuit is configured to generate output voltage signals of the output circuit. By eliminating the limit on a minimum operating power supply voltage, different high-speed data output ports are compatible, thereby improving efficiency.Type: ApplicationFiled: February 10, 2021Publication date: June 3, 2021Inventor: Kai TIAN
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Patent number: 10995367Abstract: Provided are a vesicular adaptor and a single-chain cyclic library constructed by using the adaptor. The library can be used for RNA sequencing and other sequencing platforms dependent on a single-stranded cyclic library, and has the advantage of high throughput sequencing, high accuracy and simple operations.Type: GrantFiled: September 19, 2019Date of Patent: May 4, 2021Assignee: MGI TECH CO., LTD.Inventors: Yuan Jiang, Jing Guo, Xiaojun Ji, Chunyu Geng, Kai Tian, Xia Zhao, Huaiqian Xu, Wenwei Zhang, Hui Jiang, Radoje Drmanac
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Publication number: 20210036628Abstract: A system and a method for power conversion. The system includes a rectifier; an inverter; a DC-link capacitor coupled between the rectifier and the inverter; and a controller. The controller is configured to obtain a current value at an output of the inverter and a voltage value across the DC-link capacitor, determine an average component and a fluctuating component of an output voltage of the inverter based on the obtained current value and the voltage value, and determine a current reference for controlling the rectifier based on the average component and the fluctuating component of the output voltage.Type: ApplicationFiled: October 19, 2020Publication date: February 4, 2021Inventors: Ke Dai, Derong Lin, Chengjing Li, Tian Tan, Tinho Li, Kai Tian
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Publication number: 20210006149Abstract: A power converter includes a full-bridge conversion circuit. The full-bridge conversion circuit includes a first leg and a second leg. The first leg includes at least two switches coupled to each other at a first node, and the second leg includes at least two switches coupled to each other at a second node. The power converter further includes an AC filter. The AC filter includes a first inductor, a second inductor and a capacitor. The first inductor includes a first end coupled to the first node and a second end could be couple to a grid. The second inductor includes a first end coupled to the second node and a second end could be couple to the grid. The capacitor includes a first end coupled to the second end of the first inductor and a second end coupled to the second leg. The first end of the capacitor is electrically coupled to the second end of the first inductor during a cycle of an AC voltage of the grid.Type: ApplicationFiled: September 18, 2020Publication date: January 7, 2021Inventors: Sheng Zong, Guoxing Fan, Kai Tian, Mei Liang
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Publication number: 20200080140Abstract: Provided are a vesicular adaptor and a single-chain cyclic library constructed by using the adaptor. The library can be used for RNA sequencing and other sequencing platforms dependent on a single-stranded cyclic library, and has the advantage of high throughput sequencing, high accuracy and simple operations.Type: ApplicationFiled: September 19, 2019Publication date: March 12, 2020Inventors: Yuan Jiang, Jing Guo, Xiaojun Ji, Chunyu Geng, Kai Tian, Xia Zhao, Huaiqian Xu, Wenwei Zhang, Hui Jiang, Radoje Drmanac