Abstract: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output of each converter. Each converter assesses the magnitude of its input voltage, and outputs a signal that is asserted at a time in inverse proportion to the magnitude of the input voltage. In one embodiment, producing the output signal at the asserted time comprises using the input voltage to gate a transistor whose discharge rate dictates the timing of the output signal. The two output signals arrive at an arbiter circuit whose function is to determine which output arrived at the arbiter first, as is indicative of the higher magnitude input voltage, and to set the output of the comparator accordingly.

Abstract: An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further includes delaying the clock input by an alignment magnitude to generate a first aligned phase signal and delaying each of the N delay taps by fractional amounts of the alignment magnitude to generate N phase aligned signals. A feedback loop is closed by a phase comparison between the first aligned phase signal and the cycle delay signal. The phase comparison result is used to adjust the cycle delay magnitude, which adjusts delays of the cycle delay signal and the N delay taps, and adjust the alignment magnitude, which adjusts delays of the first aligned phase signal and the N phase aligned signals.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further includes delaying the clock input by an alignment magnitude to generate a first aligned phase signal and delaying each of the N delay taps by fractional amounts of the alignment magnitude to generate N phase aligned signals. A feedback loop is closed by a phase comparison between the first aligned phase signal and the cycle delay signal. The phase comparison result is used to adjust the cycle delay magnitude, which adjusts delays of the cycle delay signal and the N delay taps, and adjust the alignment magnitude, which adjust delays of the first aligned phase signal and the N phase aligned signals.

Abstract: A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal. The time delay relationship between fine and coarse delay circuits of an adjustable delay circuit is adjusted to compensate for variations from an expected time delay relationship.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal. The time delay relationship between fine and coarse delay circuits of an adjustable delay circuit is adjusted to compensate for variations from an expected time delay relationship.

Abstract: A semiconductor memory device for distributing load of input and output lines includes: a line pre-charger for pre-charging a global read line composed of a pair of lines to a high level in an initial or steady state, a plurality of memory banks connected to a global write line for storing data provided thereto, each of which includes a memory cell array composed of a number of memory cells coupled to a multiplicity of sense amplifiers and the multiplicity of write drivers, a number of multiplexers for selecting the data from the read line; and a data input multiplexer for providing externally inputted data to the global write line on the write operation.

Abstract: A pulse generator, which only occupies a small area in a circuit chip by using a characteristic that the potential in both ends of a capacitor is maintained. The pulse generator comprises a voltage level control unit for controlling a voltage level of a first node according to the state of input signal; a first switching unit for controlling a voltage level of a second node by performing a switching operation according to the state of the input signal; a second switching unit for changing a voltage level of the second node by performing another switching operation, opposite to the first switching means according to the state of the input signal; a charge/discharge unit for charging/discharging a voltage between the first and the second nodes according to the switching state of the first and the second switching means; and an output unit for outputting a pulse signal according to the charging/discharging state of the charge/discharge means.

Abstract: The present invention discloses a method and a device for automatically performing a refresh operation, which can reduce power consumption in an auto refresh mode of a semiconductor memory device. The power consumption can be reduced by controlling the operation of input buffers or the operation of an input buffer generator for controlling the input buffers, during the auto refresh operation.

Abstract: A pulse generator, which only occupies a small area in a circuit chip by using a characteristic that the potential in both ends of a capacitor is maintained. The pulse generator comprises a voltage level control unit for controlling a voltage level of a first node according to the state of input signal; a first switching unit for controlling a voltage level of a second node by performing a switching operation according to the state of the input signal; a second switching unit for changing a voltage level of the second node by performing another switching operation, opposite to the first switching means according to the state of the input signal; a charge/discharge unit for charging/discharging a voltage between the first and the second nodes according to the switching state of the first and the second switching means; and an output unit for outputting a pulse signal according to the charging/discharging state of the charge/discharge means.

Abstract: A semiconductor memory device for distributing load of input and output lines includes: a line pre-charger for pre-charging a global read line composed of a pair of lines to a high level in an initial or steady state, a plurality of memory banks connected to a global write line for storing data provided thereto, each of which includes a memory cell array composed of a number of memory cells coupled to a multiplicity of sense amplifiers and the multiplicity of write drivers, a number of multiplexers for selecting the data from the read line; and a data input multiplexer for providing externally inputted data to the global write line on the write operation.

Abstract: A semiconductor memory device feeds back a signal made by detecting a data sensing when reading a memory chip, precharges a local data bus within a short time, performs a high-speed operation, and enhances a burst characteristic and AC characteristic responsive to the burst characteristic. The semiconductor memory device detects a sensing moment of a data generated from a local data bus in case of a read operation by using a data bus sense-amplifier unit. At this time, the detection signal precharges a local data bus and its related signals until the next data is generated.

Abstract: A pulse generating apparatus efficiently generates a pulse signal by receiving a control signal. A voltage level controller 20 receives a control signal and outputs a certain voltage through a node N0. A output level variation element C is placed between a node N0 and a node N1. A switching element 30 applies a high voltage Vcc to the node N1. A switching element 40 applies a low voltage Vss to the node N1. The pulse is generated by a logic operation of the control signal and a voltage on a node N0.