Abstract: A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.

Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from an input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates a final output clock having a phase between phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

Abstract: A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether.

Abstract: Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether.

Abstract: Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

Abstract: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.

Abstract: A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed.

Abstract: A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed.

Abstract: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.

Abstract: One delay locked loop circuit embodiment includes a delay line system configured to generate a clock output signal by adding a delay line system time delay to a clock reference signal, a phase detector, a shift register, and a control unit. The delay line system includes a coarse delay line to adjust the delay line system time delay by remote coarse-shifting, a phase selector configured to adjust the delay line system time delay by local coarse-shifting output signals from a series of local coarse delay units, and a phase mixer to adjust a particular time delay of the clock output signal by fine-shifting. The phase mixer does not receive the clock reference signal. The phase detector detects a phase difference between the clock reference signal and the clock output signal. The shift register controls the remote coarse-shifting, and the control unit controls the local coarse-shifting, based on the phase difference.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

Abstract: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.

Abstract: Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.