Abstract: A method for manufacturing a semiconductor device includes the steps of: determining a first design dimension of a gate electrode of a selection MISFET, a second design dimension of a sidewall insulating film, and initial setting conditions for ion implantation for a high-concentration semiconductor region; forming the gate electrode; measuring a first processed dimension of the gate electrode; implanting ions to form a low-concentration semiconductor region at each end of the gate electrode; forming the sidewall insulating film over a sidewall of the gate electrode; measuring a second processed dimension of the sidewall insulating film; and implanting ions to form a high-concentration semiconductor region. In the former implantation step, execution conditions to the initial setting conditions are reset according to a deviation of the first processed dimension from the first design dimension and a deviation of the second processed dimension from the second design dimension, and the step is executed.

Abstract: A magnetoresistive effect element of the present invention includes: a domain wall motion layer, a spacer layer and a reference layer. The domain wall motion layer is made of ferromagnetic material with perpendicular magnetic anisotropy. The spacer layer is formed on the domain wall motion layer and made of non-magnetic material. The reference layer is formed on the spacer layer and made of ferromagnetic material, magnetization of the reference layer being fixed. The domain wall motion layer includes at least one domain wall, and stores data corresponding to a position of the domain wall. An anisotropy magnetic field of the domain wall motion layer is larger than a value in which the domain wall motion layer can hold the perpendicular magnetic anisotropy, and smaller than an essential value of an anisotropy magnetic field of the ferromagnetic material of the domain wall motion layer.

Abstract: A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the determined transition speed, multivalued data of the read data to a read global bit line.

Abstract: A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the determined transition speed, multivalued data of the read data to a read global bit line.

Abstract: A first erase test is performed by applying an erase pulse to series of memory cells which are included in a memory cell array and which are divided into a plurality of groups until the appearance of a group for which the determination that erase is completed is made. A second erase test is performed on other series of memory cells including the series of memory cells on the basis of the number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first.

Abstract: A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.

Abstract: A magnetic memory includes a magnetic memory, including a ferromagnetic underlayer including a magnetic material, a non-magnetic intermediate layer disposed on the underlayer, a ferromagnetic data recording layer formed on the intermediate layer and having a perpendicular magnetic anisotropy, a reference layer connected to the data recording layer across a non-magnetic layer, and first and second magnetization fixed layers disposed in contact with a bottom face of the underlayer. The data recording layer includes a magnetization free region having a reversible magnetization and opposed to the reference layer, a first magnetization fixed region coupled to a first border of the magnetization free layer and having a magnetization fixed in a first direction, and a second magnetization fixed region coupled to a second border of the magnetization free layer and having a magnetization fixed in a second direction opposite to the first direction.

Abstract: A magnetic memory includes: a magnetization fixed layer having perpendicular magnetic anisotropy, a magnetization direction of the magnetization fixed layer being fixed; an interlayer dielectric; an underlayer formed on upper faces of the magnetization fixed layer and the interlayer dielectric; and a data recording layer formed on an upper face of the underlayer and having perpendicular magnetic anisotropy. The underlayer includes: a first magnetic underlayer; and a non-magnetic underlayer formed on the first magnetic underlayer. The first magnetic underlayer is formed with such a thickness that the first magnetic underlayer does not exhibit in-plane magnetic anisotropy in a portion of the first magnetic underlayer formed on the interlayer dielectric.

Abstract: A magnetoresistive effect element of the present invention includes: a domain wall motion layer, a spacer layer and a reference layer. The domain wall motion layer is made of ferromagnetic material with perpendicular magnetic anisotropy. The spacer layer is formed on the domain wall motion layer and made of non-magnetic material. The reference layer is formed on the spacer layer and made of ferromagnetic material, magnetization of the reference layer being fixed. The domain wall motion layer includes at least one domain wall, and stores data corresponding to a position of the domain wall. An anisotropy magnetic field of the domain wall motion layer is larger than a value in which the domain wall motion layer can hold the perpendicular magnetic anisotropy, and smaller than an essential value of an anisotropy magnetic field of the ferromagnetic material of the domain wall motion layer.

Abstract: The present invention is directed to providing a method for culturing cells in a system containing laminin-5. The method of the present invention is characterized by a culture system containing a polypeptide selected from a group consisting of: a protein in blood other than extracellular matrix proteins, which is, serum, serum albumin, prealbumin, immunoglobulin, ?-globulin, ?-globulin, ?1-antitrypsin (?1-AT), heptoglobin (Hp), ?2-macroglobulin (?2-M), ?-fetoprotein (AFP), transferrin, retinol-binding protein (RBP) or adiponectin; gelatin; a protein belonging to a tumor necrosis factor (TNF) family; and peptone.

Abstract: A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR (configuration register) control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads.

Abstract: A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.

Abstract: Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1?x): x (0.01?x?0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

Abstract: A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated.

Abstract: A method for manufacturing an MTJ film includes forming a first ferromagnetic layer; forming a tunnel barrier layer over the first ferromagnetic layer; and forming a second ferromagnetic layer over the tunnel barrier layer. The first ferromagnetic layer is a Co/Ni stacked film having perpendicular magnetic anisotropy. The step for forming a tunnel barrier layer includes repeating unit film formation treatment n times (n is an integer of 2 or more). The unit film formation treatment includes the steps of: depositing an Mg film by a sputtering method; and oxidizing the deposited Mg film. A film thickness of the deposited Mg film in the first unit film formation treatment is 0.3 nm or more and 0.5 nm or less. A film thickness of the deposited Mg film in the second unit film formation treatment or later is 0.1 nm or more and 0.45 nm or less.

Abstract: A magnetic memory includes: a magnetization fixed layer having perpendicular magnetic anisotropy, a magnetization direction of the magnetization fixed layer being fixed; an interlayer dielectric; an underlayer formed on upper faces of the magnetization fixed layer and the interlayer dielectric; and a data recording layer formed on an upper face of the underlayer and having perpendicular magnetic anisotropy. The underlayer includes: a first magnetic underlayer; and a non-magnetic underlayer formed on the first magnetic underlayer. The first magnetic underlayer is formed with such a thickness that the first magnetic underlayer does not exhibit in-plane magnetic anisotropy in a portion of the first magnetic underlayer formed on the interlayer dielectric.

Abstract: A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads.

Abstract: There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

Abstract: A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.

Abstract: A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated.