Abstract: An arbiter judges which of an internal access request and an external access request takes higher priority, when the internal access request conflicts with the external access request. A redundancy judgement circuit judges which of a normal memory cell and a redundancy memory cell is accessed, in accordance with each of the internal access request and the external access request. When the arbiter gives higher priority to the internal access request, the redundancy judgement circuit carries out redundancy judgement for the external access request during internal access operation. To prevent the malfunction of a memory core, a hold circuit holds redundancy judged result, and prevents the redundancy judged result for the external access request from being transmitted to the memory core that carries out the internal access operation.

Abstract: The heat resistance of a magnetic resistance device utilizing the TMR effect is improved. Also, the Neel effect of the magnetic resistance device utilizing the TMR effect is restrained. The magnetic resistance device includes a first ferromagnetic layer formed of ferromagnetic material, a non-magnetic insulative tunnel barrier layer coupled to the first ferromagnetic layer, a second ferromagnetic layer formed of ferromagnetic material and coupled to the tunnel barrier layer, and an anti-ferromagnetic layer formed of anti-ferromagnetic material. The second ferromagnetic layer is provided between the tunnel barrier layer and the anti-ferromagnetic layer. A perpendicular line from an optional position of the surface of the second ferromagnetic layer passes through at least two of the crystal grains of the second ferromagnetic layer.

Abstract: A curable composition for optical parts, including a (meth)acrylic acid ester (A) of a compound having two or more hydroxy groups in one molecule and containing no aromatic hydrocarbon structure, wherein a content of an ether structure represented by the following general formula (1): —(O—CH2—CHR1)n—??(1) wherein n is in the range of 1 to 100 and R1 is at least one selected from the group consisting of hydrogen, methyl, and ethyl, in the composition is 5% by weight or higher, and a content of sulfonic acid and/or a sulfonic acid ester in the composition is 100 ppm or lower in terms of sulfur atom content. This curable composition makes it possible to obtain optical parts by curing, which are transparent and hardly cause coloration, denaturation, and deterioration to light from a light source having an emission wavelength distribution extending from a short wavelength region of visible light to an ultraviolet region.

Abstract: A laminated ferrimagnetic thin film consists of two ferromagnetic layers and a non-magnetic intermediate layer sandwiched therebetween. The respective ferromagnetic layers are magnetically coupled in an antiferromagnetic manner through the non-magnetic intermediate layer. Each ferromagnetic layer consists of a plurality of layers. In each ferromagnetic layer, a layer which is in contact with the non-magnetic intermediate layer is formed of Co or an alloy including Co while at least one layer is formed of Ni or an alloy including Ni, and its film thickness is determined to be at least 60% or more of a film thickness of each ferromagnetic layer.

Abstract: An operation control circuit sets an inactivating timing of sense amplifiers activated in response to a read request, a write request, or a refresh request, to the timing a maximum possible quantity of signals which can be output from the sense amplifiers operating in response to the refresh request is transmitted to memory cells. Tailoring the activating period of the sense amplifiers to a refresh operation can reduce access time. A refresh control circuit generates a predetermined number of refresh requests consecutively to refresh all of the memory cells before extending the cycle of generating refresh requests. When refresh requests occur consecutively, the refresh frequency can be lowered to reduce power consumption. As a result, access time can be reduced without increasing power consumption during the standby mode.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: A plurality of switching transistors is provided, each connects power supply terminals of a plurality of first circuit blocks to a power supply line, respectively. Among the first circuit blocks, the power supply terminals of the first circuit blocks operating at different timings are connected by an internal power supply line. A power supply control circuit simultaneously turns on the switching transistors connected to the internal power supply line, in response to operation(s) of at least any one of the first circuit blocks connected to the internal power supply line. Since the switching transistors can be shared among the first circuit blocks not operating simultaneously, operation speed of the first circuit blocks can be increased. Since a total size of the switching transistors can be made small, standby current can be decreased. Accordingly, a semiconductor integrated circuit operating at a high speed can be constituted without increasing the standby current.

Abstract: A semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits activating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals or in response to activation of one of the buffer circuits at an adjacent one of the memory blocks that is located upstream along the data buses.

Abstract: A semiconductor memory device includes a data buffer for inputting/outputting data from/to an exterior of the device, a plurality of DRAM cell array blocks, an SRAM redundancy cell which is situated around each of the plurality of DRAM cell array blocks, a fuse circuit which stores therein an address of a defect memory cell in the DRAM cell array blocks, a comparison circuit which compares an input address with the address stored in the fuse circuit, and an I/O bus which couple the SRAM redundancy cell to the data buffer in response to an address match found by the comparison circuit.

Abstract: A semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits activating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals or in response to activation of one of the buffer circuits at an adjacent one of the memory blocks that is located upstream along the data buses.

Abstract: A laminated ferrimagnetic thin film consists of two ferromagnetic layers and a non-magnetic intermediate layer sandwiched therebetween. The respective ferromagnetic layers are magnetically coupled in an anti-ferromagnetic manner through the non-magnetic intermediate layer. Each ferromagnetic layer consists of a plurality of layers. In each ferromagnetic layer, a layer which is in contact with the non-magnetic intermediate layer is formed of Co or an alloy including Co while at least one layer is formed of Ni or an alloy including Ni, and its film thickness is determined to be at least 60% or more of a film thickness of each ferromagnetic layer.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: An operation control circuit sets an inactivating timing of sense amplifiers activated in response to a read request, a write request, or a refresh request, to the timing a maximum possible quantity of signals which can be output from the sense amplifiers operating in response to the refresh request is transmitted to memory cells. Tailoring the activating period of the sense amplifiers to a refresh operation can reduce access time. A refresh control circuit generates a predetermined number of refresh requests consecutively to refresh all of the memory cells before extending the cycle of generating refresh requests. When refresh requests occur consecutively, the refresh frequency can be lowered to reduce power consumption. As a result, access time can be reduced without increasing power consumption during the standby mode.

Abstract: A plurality of switching transistors is provided, each connects power supply terminals of a plurality of first circuit blocks to a power supply line, respectively. Among the first circuit blocks, the power supply terminals of the first circuit blocks operating at different timings are connected by an internal power supply line. A power supply control circuit simultaneously turns on the switching transistors connected to the internal power supply line, in response to operation(s) of at least any one of the first circuit blocks connected to the internal power supply line. Since the switching transistors can be shared among the first circuit blocks not operating simultaneously, operation speed of the first circuit blocks can be increased. Since a total size of the switching transistors can be made small, standby current can be decreased. Accordingly, a semiconductor integrated circuit operating at a high speed can be constituted without increasing the standby current.

Abstract: A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.

Abstract: A semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.

Abstract: A semiconductor integrated circuit having an active mode and a standby mode includes a node at which an internal circuit is connected to a latch circuit, the latch circuit storing a data signal output from the internal circuit. A level determination unit determines a logic level of the node in response to a control signal indicating the standby mode.

Abstract: The present invention is that, in a memory circuit comprising a cell array and peripheral circuit, the cell array power source is supplied to a circuit which operates during the power-down mode in addition to the cell array. The circuit which operates during the power-down mode is, for example, a self-refresh circuit. A dynamic memory requires refreshing operations in fixed intervals even during the power-down mode. Therefore, the self-refresh circuit is operating even during the power-down mode. Thus, by supplying the cell array power source to the self-refresh circuit, it is possible to consume a prescribed quantity of current from the cell array power source generation circuit to an extent of being able to maintain the level thereof even during the power-down mode. The cell array power source may be maintained within an appropriate voltage range thereby.

Abstract: A semiconductor memory device that can increase only the data transfer rate while the clock speed and the internal operation speed of a DDR-DRAM remain unchanged, comprising two DDR-DRAMs, in one package, commonly connected to data input/output lines to form an integrated semiconductor memory device. The semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRMAs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other.

Abstract: A semiconductor memory device includes a DQ-quantity-selection signal generation circuit which generates a DQ-quantity-selection signal indicative of a number of input/output data bits, bit lines which transfer read data and write data for memory cells, and a plurality of sense amplifiers which are connected to the bit lines, and are activated as many as indicated by the DQ-quantity-selection signal.