Abstract: A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated.

Abstract: A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section detects the temperature of the semiconductor memory. A cycle change control section sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: A laminated ferrimagnetic thin film consists of two ferromagnetic layers and a non-magnetic intermediate layer sandwiched therebetween. The respective ferromagnetic layers are magnetically coupled in an anti-ferromagnetic manner through the non-magnetic intermediate layer. Each ferromagnetic layer consists of a plurality of layers. In each ferromagnetic layer, a layer which is in contact with the non-magnetic intermediate layer is formed of Co or an alloy including Co while at least one layer is formed of Ni or an alloy including Ni, and its film thickness is determined to be at least 60% or more of a film thickness of each ferromagnetic layer.

Abstract: A laminated ferrimagnetic thin film consists of two ferromagnetic layers and a non-magnetic intermediate layer sandwiched therebetween. The respective ferromagnetic layers are magnetically coupled in an antiferromagnetic manner through the non-magnetic intermediate layer. Each ferromagnetic layer consists of a plurality of layers. In each ferromagnetic layer, a layer which is in contact with the non-magnetic intermediate layer is formed of Co or an alloy including Co while at least one layer is formed of Ni or an alloy including Ni, and its film thickness is determined to be at least 60% or more of a film thickness of each ferromagnetic layer.

Abstract: In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

Abstract: A magnetic memory is composed of: a magnetoresistance element including a free magnetic layer; a first interconnection extending in a first direction obliquely to an easy axis of the free magnetic layer; a second interconnection extending in a second direction substantially orthogonal to the first direction; and a write circuit writing data into the free magnetic layer through developing a first write current on the first interconnection, and then developing a second write current on the second interconnection with the first write current turned on. The free magnetic layer includes: first to N-th ferromagnetic layers and first to (N?1)-th non-magnetic layers with N being equal to or more than 4, the i-th non-magnetic layer being disposed between the i-th and (i+1)-th ferromagnetic layers with i being any of natural numbers equal to or less than N?1.

Abstract: After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in response to an access request, the word control circuit unselects only a word line selection signal line of a memory block selected by an external address corresponding to this access request. In each memory block, the word line selection signal line once selected is not unselected until the access request is received, so that the frequency of unselection and selection of the word line selection signal lines can be lowered. Consequently, a charge/discharge current of the word line selection signal lines can be reduced, which can reduce current consumption of a semiconductor memory.

Abstract: In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

Abstract: The heat resistance of a magnetic resistance device utilizing the TMR effect is improved. Also, the Neel effect of the magnetic resistance device utilizing the TMR effect is restrained. The magnetic resistance device includes a first ferromagnetic layer formed of ferromagnetic material, a non-magnetic insulative tunnel barrier layer coupled to the first ferromagnetic layer, a second ferromagnetic layer formed of ferromagnetic material and coupled to the tunnel barrier layer, and an anti-ferromagnetic layer formed of anti-ferromagnetic material. The second ferromagnetic layer is provided between the tunnel barrier layer and the anti-ferromagnetic layer. A perpendicular line from an optional position of the surface of the second ferromagnetic layer passes through at least two of the crystal grains of the second ferromagnetic layer.

Abstract: In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

Abstract: An equalizing circuit connects a pair of bit lines to each other in response to the activation of an equalizing control signal and connects the pair of bit lines to a precharge voltage line. An equalizing control circuit deactivates the equalizing control signal in response to the activation of a first timing signal. A word line driving circuit activates one of word lines in response to the activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after the deactivation of the equalizing control signal accompanying the activation of the first timing signal. A delay control circuit of the second signal generating circuit delays an activation timing of the second timing signal in a test mode from that in a normal mode.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: An arbiter judges which of an internal access request and an external access request takes higher priority, when the internal access request conflicts with the external access request. A redundancy judgement circuit judges which of a normal memory cell and a redundancy memory cell is accessed, in accordance with each of the internal access request and the external access request. When the arbiter gives higher priority to the internal access request, the redundancy judgement circuit carries out redundancy judgement for the external access request during internal access operation. To prevent the malfunction of a memory core, a hold circuit holds redundancy judged result, and prevents the redundancy judged result for the external access request from being transmitted to the memory core that carries out the internal access operation.

Abstract: An improved magnetic random access memory (MRAM) has two sets of signal lines where each set is substantially perpendicular to the other, and memory cells located at the intersections of the signal lines. Each memory cell has a magneto-resistant element containing a magnetization layer whose magnetic characteristics change depending on the intensity of the magnetic field applied. A desired magnetic field can be applied to any cell by supplying appropriate write currents to the signal lines intersecting at that cell. The relationship between applied magnetic fields, two different threshold function values, and four different magnetic fields that result at each cell is disclosed. Better performance, namely, improved selectivity and a more stable write operation, results.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A magnetic memory is composed of: a magnetoresistance element including a free magnetic layer; a first interconnection extending in a first direction obliquely to an easy axis of the free magnetic layer; a second interconnection extending in a second direction substantially orthogonal to the first direction; and a write circuit writing data into the free magnetic layer through developing a first write current on the first interconnection, and then developing a second write current on the second interconnection with the first write current turned on. The free magnetic layer includes: first to N-th ferromagnetic layers and first to (N?1)-th non-magnetic layers with N being equal to or more than 4, the i-th non-magnetic layer being disposed between the i-th and (i+1)-th ferromagnetic layers with i being any of natural numbers equal to or less than N?1.

Abstract: A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.