Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract: A highly localized diffusion barrier is incorporated into a polysilicon line to allow the doping of the polysilicon layer without sacrificing an underlying material layer. The diffusion barrier is formed by depositing a thin polysilicon layer and exposing the layer to a nitrogen-containing plasma ambient. Thereafter, the deposition is resumed to obtain the required final thickness. Moreover, a polysilicon line is disclosed, having a highly localized barrier layer.

Abstract: By forming a buried nickel silicide layer followed by a cobalt silicide layer in silicon-containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: By forming an implantation mask prior to the definition of the drain and the source areas, an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask, the lateral dimension of the gate electrode may be defined by well-established sidewall spacer techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.

Abstract: By maintaining the gate electrode covered during the process flow for forming metal silicide regions in the drain and source of a field effect transistor, an appropriate metal silicide may be formed on the gate electrode which meets the requirement for aggressive gate length scaling. Preferably, a nickel silicide is formed on the gate electrode, whereas the drain and source regions receive the well-established cobalt disilicide. Additionally, the gate electrode dopant profile is effectively decoupled from the drain and source dopant profile.

Abstract: According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions and the gate electrode of a field effect transistor, allows the formation of nickel silicide, which is substantially thermally stable up to temperatures of 500° C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.

Abstract: The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

Abstract: A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

Abstract: The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

Abstract: The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Abstract: A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.

Abstract: A test structure for assessing the reliability of a dielectric of a circuit element in an integrated circuit includes a plurality of test circuit elements and a plurality of contact pads, wherein at least some of the test circuit elements share one or more of the contact pads. In this way, a failure event can be detected with a reduced number of contact pads, thereby significantly reducing the area of floor space occupied by the test structure.

Abstract: The present invention provides a technique for forming extremely thin insulation layers requiring the incorporation of specified amounts of nitrogen, wherein the effect of nitrogen variations across the substrate surface may be reduced in that during and/or after the nitrogen incorporation an oxidation process is performed. The nitrogen variations lead to a nitrogen concentration dependent oxidation rate and, hence, a nitrogen concentration dependent thickness variation of the insulating layer. In particular, the threshold variations of transistors including the thin insulating layer as a gate insulation layer may effectively be reduced.

Abstract: A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.