Patents by Inventor Katherine H. Chiang

Katherine H. Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022934
    Abstract: Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Kuo-Chang Chiang, Katherine H. cHIANG, Yen-Chung Ho, Ming-Yen Chuang, Chung-Te Lin
  • Publication number: 20250015191
    Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a barrier dielectric layer, a transistor and a first barrier. The barrier dielectric layer has an upper surface and a lower surface. The transistor is partially formed in the barrier dielectric layer and includes an electrode element, and the electrode element has a first lateral surface, wherein the first lateral surface extends from the upper surface toward the lower surface. The first barrier covers the entirety of the first lateral surface of the electrode element.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao HUANG, Tzu-Hsiang HSU, Kuo-Chang CHIANG, Katherine H. CHIANG
  • Publication number: 20250017016
    Abstract: Some embodiments relate to an integrated circuit including first and second charge-trapping devices and a control circuit. The first charge-trapping device includes a first charge-trapping structure arranged over a substrate between a first gate structure and a first channel region. The second charge-trapping device is coupled in series with the first charge-trapping device and includes a second charge-trapping structure arranged over the substrate between a second gate structure and a second channel region. The control circuit is coupled to the first and second gate structures and is configured to store a first input of an IMPLY operation as a stored value of the first charge-trapping device, store a second input of the IMPLY operation as a stored value of the second charge-trapping device, and update the stored value of the second charge-trapping device based on the stored value of the first charge-trapping device to perform the IMPLY operation.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: Yun-Feng Kao, Katherine H. Chiang
  • Publication number: 20250006505
    Abstract: A method for manufacturing a semiconductor structure includes: forming an interconnect level structure having a first device region, a first side region aside the first device region, a second device region and a second side region aside the second device region; forming a dielectric layer over the interconnect structure, the dielectric layer including a first dielectric portion, a second dielectric portion, a first patterned portion and a second patterned portion that are respectively formed over the first device region, the second device region, the first side region, and the second side region, the first patterned portion and the second patterned portion being formed with different patterns; performing a planarization process on the dielectric layer; forming first recesses and second recesses respectively in the planarized first dielectric portion and the planarized second dielectric portion; and forming contact portion respectively in the first recesses and the second recesses.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hsiang HSU, Sun-Yi CHANG, Katherine H. CHIANG
  • Patent number: 12176286
    Abstract: A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Shyue Lai, Chien-Hao Huang, Chia-Yu Ling, Katherine H Chiang, Chung-Te Lin
  • Patent number: 12176022
    Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Jun Wu, Yun-Feng Kao, Sheng-Chih Lai, Katherine H. Chiang, Chung-Te Lin
  • Publication number: 20240421036
    Abstract: A semiconductor device may include a non-volatile memory structure that may be formed in a back end of line (BEOL) region of a semiconductor device. The non-volatile memory structure may include a dielectric-based one-time programmable (OTP) anti-fuse memory structure or a dielectric-based resistive random access memory (ReRAM), among other examples. The non-volatile memory structure may be selectively programmed based on modifying an electrical resistance of the non-volatile memory structure, and may retain data stored in the non-volatile memory structure even when electrical power is removed from the semiconductor device.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Yun-Feng KAO, Katherine H. CHIANG
  • Patent number: 12171106
    Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin
  • Publication number: 20240413247
    Abstract: A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 12, 2024
    Inventors: Kuo-Chang Chiang, Katherine H. Chiang, Yen-Chung Ho, Ming-Yen Chuang, Chung-Te Lin
  • Publication number: 20240395824
    Abstract: An embodiment inverter circuit includes an electrically insulating structure having a slab geometry including a first surface and a second surface that are parallel to one another and that are each oriented in respective planes that are perpendicular to a thickness direction, a p-type semiconductor layer formed on the first surface, an n-type semiconductor layer formed on the second surface, a gate dielectric layer formed in contact with the p-type semiconductor layer and the n-type semiconductor layer, a gate electrode formed in contact with the gate dielectric layer, a first source electrode and a first drain electrode formed in contact with the p-type semiconductor layer, and a second source electrode and a second drain electrode formed in contact with the n-type semiconductor layer. The inverter circuit may be connected to a voltage supply, a ground voltage terminal, an input signal terminal, and an output terminal to operate as an inverter.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Inventors: Yun-Feng Kao, Katherine H. Chiang
  • Publication number: 20240396749
    Abstract: The present disclosure describes embodiments of a device with memory and a processor. The memory is configured to store integrated circuit (IC) trim and redundancy information. The processor is configured to extract bits from the IC trim and redundancy information, perform a hashing function on the extracted bits to generate hashed bits, and in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits. In some embodiments, the memory that stores the IC trim and redundancy information can be different from other memory used by the device for other operations (e.g., accessing user data and program data that have been written into system memory).
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine H. Chiang, Shih-Lien Linus Lu
  • Publication number: 20240395322
    Abstract: A semiconductor device includes an array of M inverters, M being an integer of at least 2 such that the array of M inverters includes at least a first inverter and a second inverter; (M?1) pairs of resistive memory devices (RMDs) coupled to the array of M inverters; and a write line coupled to an input of the first inverter. (M?1) inverters of the array of M inverters are each connected in parallel with a pair of RMDs of the (M?1) pairs of RMDs.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Yun-Feng KAO, Katherine H. CHIANG
  • Publication number: 20240386957
    Abstract: In some embodiments, the present disclosure relates to a memory device, including a plurality of content addressable memory (CAM) units arranged in rows and columns and configured to store a plurality of data states, respectively. A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units, and a plurality of match lines extending along the columns and configured to output a plurality of match signals, respectively from respective columns of CAM units. A match signal of a column is asserted when the data states of the respective CAM units of the column match corresponding bits of the search query.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventor: Katherine H. Chiang
  • Publication number: 20240387542
    Abstract: A semiconductor device includes a first gate, a second gate disposed over the first gate, a first contact, a second contact, a third contact disposed between the first gate and the second gate, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer is disposed between the first gate and the third contact. The first semiconductor layer includes a first channel region, a first source region, and a first drain region, and the first channel region laterally extends between the first drain region and the first contact. The second semiconductor layer is disposed between the second gate and the third contact. The second semiconductor layer includes a second channel region, a second source region, and a second drain region, and the second channel region laterally extends between the second drain region and the second contact.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Feng Kao, Katherine H. CHIANG
  • Publication number: 20240387619
    Abstract: A method for manufacturing a stacked capacitor structure includes: forming a first patterned structure over a substrate; forming a first bottom electrode over the first patterned structure; depositing a first dielectric film over the first bottom electrode; depositing a first top electrode layer over the first dielectric film; forming a first vertical interconnect structure; forming a second patterned structure over the first top electrode layer; forming a second bottom electrode over the second patterned structure and electrically connected to the first bottom electrode through the first vertical interconnect structure; depositing a second dielectric film over the second bottom electrode; depositing a second top electrode layer over the second dielectric film; and forming a second vertical interconnect structure extending from the first top electrode layer. The second top electrode layer is electrically connected to the first top electrode layer through the second vertical interconnect structure.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yu LAI, Katherine H. CHIANG
  • Publication number: 20240383048
    Abstract: A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 21, 2024
    Inventors: Gao-Ming WU, Katherine H. CHIANG, Chien-Hao HUANG, Chung-Te LIN
  • Publication number: 20240387753
    Abstract: The present disclosure describes an embodiment of a thin film transistor based light sensor circuit. The thin film transistor based light sensor circuit includes two thin film transistors, in which a channel region of one of the thin film transistors includes a light sensing area and a channel region of the other thin film transistor has a capping material disposed thereon. The thin film transistor based light sensor circuit further includes a comparator device electrically coupled to the two thin film transistors and configured to detect a current difference between the thin film transistors in response to the thin film transistor with the channel region having the light sensing area being exposed to light.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Katherine H. Chiang
  • Publication number: 20240387108
    Abstract: A capacitor structure includes a first electrode, a second electrode, a dielectric layer between the first electrode and the second electrode, a first oxygen donor layer between the dielectric layer and the first electrode, a second oxygen donor layer between the dielectric layer and the second electrode, a first conductive layer between the first oxygen donor layer and the dielectric layer, and a second conductive layer between the second oxygen donor layer and the dielectric layer. An oxygen concentration of the first oxygen donor layer increases. An oxygen concentration of the second oxygen donor layer increases. A metal atom of the first electrode and a metal atom of the second electrode are different from a metal atom of the first oxygen donor layer and different from a metal atom of the second oxygen donor layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: HSIN-YU LAI, KATHERINE H. CHIANG
  • Publication number: 20240385056
    Abstract: The present disclosure describes an embodiment of a thin film transistor based temperature sensor circuit. The thin film transistor based temperature sensor circuit includes a first frequency generator with thin film transistors, a second frequency generator with complementary metal oxide semiconductor transistors, first and second counter devices, and a processor device. The first and second counter devices are configured to count a number of first pulses and a number of second pulses from the first frequency generator and second frequency generator, respectively. The processor device is configured to determine a frequency based on the number of first and second pulses.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Lien Linus LU, Katherine H. CHIANG
  • Patent number: 12146798
    Abstract: The present disclosure describes an embodiment of a thin film transistor based temperature sensor circuit. The thin film transistor based temperature sensor circuit includes a first frequency generator with thin film transistors, a second frequency generator with complementary metal oxide semiconductor transistors, first and second counter devices, and a processor device. The first and second counter devices are configured to count a number of first pulses and a number of second pulses from the first frequency generator and second frequency generator, respectively. The processor device is configured to determine a frequency based on the number of first and second pulses.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Katherine H. Chiang