Abstract: A method of manufacturing a memory cell includes the following steps. A channel material is formed to contact a source line and a bit line. A ferroelectric (FE) material is formed to contact the channel material. A word line is formed to contact the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.

Abstract: A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.

Abstract: The present disclosure describes embodiments of a device with memory and a processor. The memory is configured to store integrated circuit (IC) trim and redundancy information. The processor is configured to extract bits from the IC trim and redundancy information, perform a hashing function on the extracted bits to generate hashed bits, and in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits. In some embodiments, the memory that stores the IC trim and redundancy information can be different from other memory used by the device for other operations (e.g., accessing user data and program data that have been written into system memory).

Abstract: In some embodiments, the present disclosure relates to a memory device, including a plurality of content addressable memory (CAM) units arranged in rows and columns and configured to store a plurality of data states, respectively. A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units, and a plurality of match lines extending along the columns and configured to output a plurality of match signals, respectively from respective columns of CAM units. A match signal of a column is asserted when the data states of the respective CAM units of the column match corresponding bits of the search query.

Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.

Abstract: A semiconductor structure includes a sensor, a patterned dielectric layer, and a cover disposed on the patterned dielectric layer. The sensor includes a bio-sensing device and at least one voltage-reference device disposed in proximity to the bio-sensing device. The bio-sensing device includes a first field effect transistor (FET) and a first sensing portion of a sensing film capacitively coupled to the first FET, and the first sensing portion is concave toward the first FET. The at least one voltage-reference device includes a second FET and a second sensing portion of the sensing film capacitively coupled to the second FET. The patterned dielectric layer is disposed on the sensing film and includes at least one sensing well located above the at least one voltage-reference device and the bio-sensing device. The cover includes fluid channels communicating with the at least one sensing wells.

Abstract: An integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate and includes a first dielectric layer and a memory module. The memory module includes a first memory device, a second memory device, and a third memory device. The first memory device is embedded in the first dielectric layer. The second memory device is disposed aside the first memory device and is embedded in the first dielectric layer. The first memory device, the second memory device, and the third memory device are different types of memory devices.

Abstract: A semiconductor structure includes an isolation structure penetrating through a semiconductor substrate, a biosensor coupled to the semiconductor substrate, and a cover. The biosensor includes a bio-sensing device, a voltage-reference device spaced apart from the bio-sensing device, thermal management devices in proximity to the bio-sensing device, and a patterned dielectric layer. Each of the bio-sensing and voltage-reference devices includes a gate structure disposed on a bottom surface of the semiconductor substrate, S/D regions disposed in the semiconductor substrate, and a portion of a sensing film disposed on the semiconductor substrate and capacitively coupled to the gate structure and the S/D regions. Each thermal management devices includes a gate structure underlying the isolation structure or the semiconductor substrate. The patterned dielectric layer overlying the semiconductor substrate includes sensing wells located above the voltage-reference and bio-sensing devices.

Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

Abstract: A semiconductor structure is provided. The semiconductor structure may include a transistor structure, the transistor structure may include a gate region arranged over an upper surface of a substrate and extending substantially in a first direction that is perpendicular to the upper surface of the substrate; a first source/drain region over the upper surface of the substrate; a second source/drain region over the upper surface of the substrate; and a channel region vertically extending in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers a sidewall of the channel region.

Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.

Abstract: A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.

Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature, and while the NVM array is heated to the target temperature, programming a subset of the NVM cells to first resistance levels and obtaining a first current distribution, programming the subset of NVM cells to second resistance levels and obtaining a second current distribution, calculating a current threshold level from the first and second current distributions, and for each of the NVM cells, programing the NVM cell to one of the first or second resistance levels, and using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level. A bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the first and second P/F status of each of the NVM cells.

Abstract: In some embodiments, the present disclosure relates to a memory device, including a plurality of content addressable memory (CAM) units arranged in rows and columns and configured to store a plurality of data states, respectively. A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units, and a plurality of match lines extending along the columns and configured to output a plurality of match signals, respectively from respective columns of CAM units. A match signal of a column is asserted when the data states of the respective CAM units of the column match corresponding bits of the search query.

Abstract: A biosensor including a first sensor, a second sensor, a patterned dielectric layer and a cover is provided. The first sensor includes a first voltage-reference device and a first bio-sensing device. The second sensor is disposed adjacent to the first sensor, the second sensor includes a second voltage-reference device and a second bio-sensing device, the first sensor is spaced apart from the second sensor by a lateral distance, and the lateral distance is greater than a half of an average lateral dimension of the first voltage-reference device and the second voltage-reference device. The patterned dielectric layer includes sensing wells located above the first voltage-reference device, the first bio-sensing device, the second voltage-reference device and the second bio-sensing device. The cover includes fluid channels communicating with the sensing wells.

Abstract: Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).

Abstract: A memory device includes a first transistor and a second transistor. Each of the first and second transistors includes a first source/drain electrode, a second source/drain electrode, a channel feature, a gate dielectric and a gate electrode. The second source/drain electrode is coplanar with the first source/drain electrode. The channel feature is disposed between and interconnects the first and second source/drain electrodes. The gate dielectric is disposed over the channel feature. The gate electrode is disposed over the gate dielectric, and overlaps the channel feature. The second transistor is disposed over the first transistor. The first source/drain electrode of the second transistor is connected to the gate electrode of the first transistor.