Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first transistor, and a second transistor. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. The first transistor includes a gate structure. The second transistor is disposed adjacent to the first transistor, and includes a source/drain structure. The gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the second metal line layer through the third metal line layer. A manufacturing method of a semiconductor structure is also provided.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a magnetic tunnel junction (MTJ) disposed on a first electrode that is within a dielectric structure over a substrate. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector and the second unipolar selector have different widths.

Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Abstract: A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Abstract: Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).

Abstract: Various embodiments of the present application are directed towards a memory device including a memory cell. The memory cell includes a plurality of semiconductor devices disposed on a substrate. A lower inter-metal dielectric (IMD) structure overlies the semiconductor devices. A plurality of conductive vias and a plurality of conductive wires are disposed within the IMD structure and are electrically coupled to the semiconductor devices. A data backup unit overlies the plurality of conductive vias and wires. The data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer, a first memory gate structure, and a second memory gate structure. The first and second memory gate structures include an upper gate electrode over a ferroelectric layer. The first and second source/drain structures are directly electrically coupled to the semiconductor devices by way of the conductive vias and wires.

Abstract: A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i-1×C. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.

Abstract: An active device, a semiconductor device and a semiconductor chip are provided. The active device includes: a channel layer; a top source/drain electrode, disposed at a top side of the channel layer; a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the channel layer; a first gate structure and a second gate structure, located between the top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer; and a third gate structure and a fourth gate structure, located between the top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer.

Abstract: A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.

Abstract: In some embodiments, the present disclosure relates to a memory device, including a plurality of content addressable memory (CAM) units arranged in rows and columns and configured to store a plurality of data states, respectively. A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units, and a plurality of match lines extending along the columns and configured to output a plurality of match signals, respectively from respective columns of CAM units. A match signal of a column is asserted when the data states of the respective CAM units of the column match corresponding bits of the search query.

Abstract: Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.

Abstract: Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

Abstract: A method includes generating an ECC encoded output data by executing an ECC-Space operation using an ECC encoded first data from a memory as a first operand and an ECC encoded second data from the memory as a second operand. The ECC-Space operation is translated from a two operands operation that is operative to transform a first data and a second data into a third data. A result of encoding the first data is the ECC encoded first data and a result of encoding the second data is the ECC encoded second data if the first data and the second data are encoded with an ECC algorithm. The method also includes storing the ECC encoded output data to the memory. The ECC encoded output data is identical to a result of encoding the third data if the third data is encoded with the ECC algorithm.

Abstract: A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

Abstract: A memory system including a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The plurality of memory cells are arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, and a source. In the plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row. In the plurality of bit lines and the plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, where each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column.

Abstract: A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.

Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer and a gate dielectric layer may be formed over the plurality of vertical stacks. Sacrificial spacers are formed around the plurality of vertical stacks. At least one dielectric wall structure may be formed around the sacrificial spacers by filling gaps between neighboring pairs of the sacrificial spacers with a dielectric fill material. The sacrificial spacers are replaced with gate electrodes. Each of the gate electrodes may laterally surround a respective row of vertical stacks that are arranged along a first horizontal direction.