Patents by Inventor Katsuaki Natori

Katsuaki Natori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9196335
    Abstract: According to one embodiment, a magnetic memory includes magnetoresistive effect elements each including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer which are successively stacked, and a ferroelectric capacitor provided above the magnetoresistive effect elements via an insulating layer, and including a lower electrode, a ferroelectric film, and an upper electrode which are successively stacked.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki Natori, Koji Yamakawa
  • Patent number: 9070866
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the tunnel barrier layer. The tunnel barrier includes a nonmagnetic oxide having a spinel structure. Oxides forming the spinel structure are combined such that a single phase is formed by a solid phase in a component ratio region including a component ratio corresponding to the spinel structure and having a width of not less than 2%.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: June 30, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Nagamine, Daisuke Ikeno, Katsuya Nishiyama, Katsuaki Natori, Koji Yamakawa
  • Patent number: 8982614
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier provided on the first ferromagnetic layer, and a second ferromagnetic layer provided on the tunnel barrier. The tunnel barrier includes a nonmagnetic mixture containing MgO and a metal oxide with a composition which forms, in a solid phase, a single phase with MgO.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Nagamine, Daisuke Ikeno, Katsuya Nishiyama, Katsuaki Natori, Koji Yamakawa
  • Publication number: 20140284732
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the tunnel barrier layer. The tunnel barrier includes a nonmagnetic oxide having a spinel structure. Oxides forming the spinel structure are combined such that a single phase is formed by a solid phase in a component ratio region including a component ratio corresponding to the spinel structure and having a width of not less than 2%.
    Type: Application
    Filed: August 7, 2013
    Publication date: September 25, 2014
    Inventors: Makoto NAGAMINE, Daisuke IKENO, Katsuya NISHIYAMA, Katsuaki NATORI, Koji YAMAKAWA
  • Publication number: 20140284592
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier provided on the first ferromagnetic layer, and a second ferromagnetic layer provided on the tunnel barrier. The tunnel barrier includes a nonmagnetic mixture containing MgO and a metal oxide with a composition which forms, in a solid phase, a single phase with MgO.
    Type: Application
    Filed: August 8, 2013
    Publication date: September 25, 2014
    Inventors: Makoto NAGAMINE, Daisuke IKENO, Katsuya NISHIYAMA, Katsuaki NATORI, Koji YAMAKAWA
  • Publication number: 20140269033
    Abstract: According to one embodiment, a magnetic memory includes magnetoresistive effect elements each including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer which are successively stacked, and a ferroelectric capacitor provided above the magnetoresistive effect elements via an insulating layer, and including a lower electrode, a ferroelectric film, and an upper electrode which are successively stacked.
    Type: Application
    Filed: August 8, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki NATORI, Koji YAMAKAWA
  • Patent number: 8741161
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Sonoda, Kyoichi Suguro, Masatoshi Yoshikawa, Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno
  • Publication number: 20140117478
    Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Patent number: 8710604
    Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Tadashi Kai
  • Publication number: 20140085971
    Abstract: According to one embodiment, a magnetoresistive effect element includes the following structure. A first ferromagnetic layer has a variable magnetization direction. A second ferromagnetic layer has an invariable magnetization direction. A tunnel barrier layer is formed between the first and second ferromagnetic layers. An energy barrier between the first ferromagnetic layer and the tunnel barrier layer is higher than an energy barrier between the second ferromagnetic layer and the tunnel barrier layer. The second ferromagnetic layer contains a main component and an additive element. The main component contains at least one of Fe, Co, and Ni. The additive element contains at least one of Mg, Al, Ca, Sc, Ti, V, Mn, Zn, As, Sr, Y, Zr, Nb, Cd, In, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, and W.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 27, 2014
    Inventors: Makoto NAGAMINE, Daisuke IKENO, Koji UEDA, Katsuya NISHIYAMA, Katsuaki NATORI, Koji YAMAKAWA
  • Patent number: 8653614
    Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Patent number: 8609487
    Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto, Katsuyuki Sekine, Ryota Fujitsuka, Daisuke Nishida, Yoshio Ozawa
  • Patent number: 8604573
    Abstract: According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Yasuyuki Sonoda
  • Patent number: 8587043
    Abstract: According to one embodiment, a magnetoresistive random access memory includes a magnetoresistive element in a memory cell, the magnetoresistive element including a first metal magnetic layer, a second metal magnetic layer, and an insulation layer interposed between the first and second metal magnetic layers. An area of each of the first and second metal magnetic layers is smaller than an area of the insulation layer.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Koji Yamakawa, Daisuke Ikeno
  • Publication number: 20130249025
    Abstract: According to one embodiment, a magnetoresistive element includes a bottom electrode, a first magnetic layer with an magnetic axis substantially perpendicular to a film plane thereof, a first interface layer, an MgO insulating layer, a second interface layer, a second magnetic layer with an magnetic axis nearly perpendicular to a film plane thereof, and a top electrode. The magnetoresistive element has a diffusion barrier layer between the first magnetic layer and the first interface layer when the first magnetic layer contains Pt or Pd, and a diffusion barrier layer between the second magnetic layer and the second interface layer when the second magnetic layer contains Pt or Pd. The diffusion barrier layer is an Hf film of thickness 0.6 nm to 0.8 nm.
    Type: Application
    Filed: September 8, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki NATORI, Toshihiko Nagase, Eiji Kitagawa, Tadashi Kai
  • Patent number: 8410529
    Abstract: According to one embodiment, a semiconductor device, includes a magneto resistive element including a first magnetic layer, a first interface magnetic layer, a nonmagnetic layer, a second interface magnetic layer and a second magnetic layer as a stacked structure in order; and a metal layer including first metal atoms, second metal atoms and boron atoms, the metal layer being provided at least one region selected from under the first magnetic, between the first magnetic layer and the first interface magnetic layer, between the second interface magnetic layer and the second magnetic layer, and upper the second magnetic layer.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Publication number: 20130001715
    Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first interfacial magnetic layer on the first magnetic layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second magnetic layer on the second interfacial magnetic layer; and an upper electrode layer on the second magnetic layer. Either the first magnetic and interfacial magnetic layers or the second magnetic and interfacial magnetic layers constitute a storage layer. The other layers of the first magnetic and interfacial magnetic layers and the second magnetic and interfacial magnetic layers constitute a reference layer. The lower electrode includes an alloy layer or mixture layer of a precious metal and a transition element or a rare earth element, or comprises a conductive oxide layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: January 3, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji YAMAKAWA, Katsuaki NATORI, Daisuke IKENO
  • Publication number: 20130001716
    Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: January 3, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Tadashi Kai
  • Publication number: 20130005148
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.
    Type: Application
    Filed: March 23, 2012
    Publication date: January 3, 2013
    Inventors: Yasuyuki Sonoda, Kyoichi Suguro, Masatoshi Yoshikawa, Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno
  • Publication number: 20120326252
    Abstract: According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.
    Type: Application
    Filed: March 20, 2012
    Publication date: December 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Yasuyuki Sonoda