Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.

Abstract: A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode provided above the charge storage layer, a second insulating film provided between the control gate electrode and the charge storage layer, the second insulating film between adjacent charge storage layers including a first region having permittivity lower than that of the second insulating film on a top surface of the charge storage layer in a cross-section view of a channel width direction of the nonvolatile memory cell, and the first region having composition differing from that of the second insulating film on the top surface of the charge storage layer.

Abstract: A semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a charge storage layer on the tunnel insulating film, a block insulating film on the charge storage layer, and a control gate electrode on the block insulating film, the charge storage layer including a plurality of layers including first and second charge storage layers, the second charge storage layer being provided on a nearest side of the block insulating film, the first charge storage layer being provided between the tunnel insulating film and the second charge storage layer, the second charge storage layer having a higher trap density than the first charge storage layer, the second charge storage layer having a smaller band gap than the first charge storage layer, and the second charge storage layer having a higher permittivity than the first charge storage layer and a silicon nitride film.

Abstract: A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.

Abstract: In a nonvolatile semiconductor memory device where a tunnel insulating film, a charge storage layer, a blocking insulating film, and a control gate are stacked one on top of another on a semiconductor substrate, with an element isolation insulating film buried between adjacent cells, a barrier layer composed of at least one of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film which has a higher density than that of the element isolation insulating film is provided at the interface between the element isolation insulating film and the blocking insulating film or between the element isolation film and the control gate.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a capacitor which is disposed above the semiconductor substrate and in which a dielectric film is held between lower and upper electrodes, an oxide film formed in such a manner as to coat the capacitor and having a thickness of 5 nm or more and 50 nm or less, and a protective film formed on the oxide film by an ALD process.

Abstract: A semiconductor device includes an element region having a channel region, and a unit gate structure inducing a channel in the channel region, the unit gate structure including a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge storage insulating film, and a control gate electrode formed on the block insulating film, wherein a distance between the element region and the control gate electrode is shorter at a center portion of the unit gate structure than at both ends thereof, as viewed in a section parallel to a channel width direction.

Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate, and including a bottom electrode, a dielectric film formed on the bottom electrode, and a top electrode formed on the dielectric film and having a plurality of hole patterns.

Abstract: A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.

Abstract: A method of forming an insulating film includes forming a base film comprising a material whose surface is oxidized by being exposed to an oxidant. A source gas containing a metal material and a first oxidant having a first oxidation force are alternately supplied to form a first insulating film on the base film. A source gas containing a metal material and a second oxidant having a second oxidation force stronger than the first oxidation force are alternately supplied to form a second insulating film on the first insulating film.

Abstract: A semiconductor device according to an aspect of the present invention comprises a semiconductor substrate, a ferroelectric capacitor, a protective film and an auxiliary capacitor. The ferroelectric capacitor is provided above the semiconductor substrate and comprises an upper electrode, a lower electrode and a ferroelectric film interposed between the upper and lower electrodes. The protective film is formed, covering the ferroelectric capacitor. The auxiliary capacitor is provided in a circuit section peripheral to the ferroelectric capacitor and uses the protective film as capacitor insulating film.

Abstract: A semiconductor memory device having a cell size of 60 nm or less includes a tunnel insulation film formed in a channel region of a silicon substrate containing a burying insulation film, a first conductive layer formed on the tunnel insulation film, an inter-electrode insulation film formed on the burying insulation film and the first conductive layer, a second conductive layer formed on the inter-electrode insulation film, a side wall insulation film formed on the side walls of the first conductive layer, the second conductive layer, and the inter-electrode insulation film, and an inter-layer insulation film formed on the side wall insulation film. The tunnel insulation film or the inter-electrode insulation film contains a high-dielectric insulation film. The side wall insulation film contains a predetermined concentration of carbon and nitrogen as well as chlorine having a concentration of 1×1019 atoms/cm3 or less.

Abstract: A semiconductor memory device of an aspect of the present invention comprises a plurality of memory cell transistors arranged in a memory cell array, a select transistor which is disposed in the memory cell array and which selects the memory cell transistor, and a peripheral circuit transistor provided in a peripheral circuit which controls the memory cell array, the memory cell transistor including a gate insulating film provided on a semiconductor substrate, a floating gate electrode provided on the gate insulating film, a between-storage-layer-and-electrode insulating film which is provided on the floating gate electrode and through which the amount of passing charge is greater than that through the gate insulating film during the application of an electric field in write and erase operations of the semiconductor memory, and a control gate electrode on the between-storage-layer-and-electrode insulating film.

Abstract: A semiconductor device includes a semiconductor substrate having a device formation region, a tunnel insulating film formed on the device formation region, a floating gate electrode formed on the tunnel insulating film, isolation insulating films which cover side surfaces of the device formation region, side surfaces of the tunnel insulating film, and side surfaces of a lower portion of the floating gate electrode, an inter-electrode insulating film which covers an upper surface and side surfaces of an upper portion of the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein upper corner portions of the floating gate electrode are rounded as viewed from a direction parallel with the upper surface and the side surfaces of the upper portion of the floating gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.

Abstract: A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrode.

Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.

Abstract: A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.

Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.