Patents by Inventor Katsuaki Natori

Katsuaki Natori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7122851
    Abstract: A semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate, and including a bottom electrode, a top electrode and a dielectric film between the bottom and top electrodes, the bottom electrode including a conductive film selected from a noble metal film and a noble metal oxide film, a metal oxide film having a perovskite structure, provided between the dielectric film and the conductive film, expressed by ABO3, and containing first metal element as B-site element, and a metal film provided between the conductive film and the metal oxide film, and containing second metal element which is B-site element of a metal oxide having a perovskite structure, a decrease of Gibbs free energy when the second metal element forms oxide being larger than that when the first metal element forms oxide, a thickness of the metal oxide film being 5 nm or less.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Koji Yamakawa, Katsuaki Natori
  • Patent number: 7105400
    Abstract: There is disclosed a method of manufacturing a semiconductor device, comprising forming an underlying region including an interlevel insulating film on a semiconductor substrate, forming an alumina film on the underlying region, forming a hole in the alumina film, filling the hole with a bottom electrode film, forming a dielectric film on the bottom electrode film, and forming a top electrode film on the dielectric film.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 12, 2006
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AG
    Inventors: Keitaro Imai, Koji Yamakawa, Hiroshi Itokawa, Katsuaki Natori, Osamu Arisumi, Keisuke Nakazawa, Bum-ki Moon
  • Patent number: 7091538
    Abstract: A semiconductor device comprises a semiconductor substrate including a diffusion area, a capacitor provided above the semiconductor substrate and including a lower electrode, a dielectric film, and an upper electrode, a plug provided between the semiconductor substrate and the capacitor and having a lower end connected to the diffusion area and an upper end connected to the lower electrode, and a dummy plug provided between the semiconductor substrate and the capacitor and having a lower end not connected to the diffusion area and an upper end connected to the lower electrode.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya
  • Patent number: 7022580
    Abstract: A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrodes.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: April 4, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Tomohiro Saito, Yoshihiro Uozumi
  • Publication number: 20060038215
    Abstract: A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrode.
    Type: Application
    Filed: October 25, 2005
    Publication date: February 23, 2006
    Inventors: Katsuaki Natori, Tomohiro Saito, Yoshihiro Vozumi
  • Publication number: 20050255663
    Abstract: A semiconductor device according to the present invention comprises a capacitor including a lower electrode, a dielectric material, and an upper electrode. The device further comprises a first protective film which contacts the upper electrode to constitute a columnar structure of films formed by a sputtering process and a second protective film formed above the first protective film by a CVD process.
    Type: Application
    Filed: June 1, 2004
    Publication date: November 17, 2005
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya, Karl Hornik, Andreas Hiliger
  • Publication number: 20050230728
    Abstract: A semiconductor device according to an aspect of the present invention comprises a semiconductor substrate, a ferroelectric capacitor, a protective film and an auxiliary capacitor. The ferroelectric capacitor is provided above the semiconductor substrate and comprises an upper electrode, a lower electrode and a ferroelectric film interposed between the upper and lower electrodes. The protective film is formed, covering the ferroelectric capacitor. The auxiliary capacitor is provided in a circuit section peripheral to the ferroelectric capacitor and uses the protective film as capacitor insulating film.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 20, 2005
    Inventors: Katsuaki Natori, Soichi Yamazaki, Koji Yamakawa, Hiroyuki Kanaya
  • Publication number: 20050212036
    Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 29, 2005
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Hirokazu Ishida, Katsuaki Natori, Seiji Inumiya
  • Publication number: 20050212028
    Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate, and including a bottom electrode, a dielectric film formed on the bottom electrode, and a top electrode formed on the dielectric film and having a plurality of hole patterns.
    Type: Application
    Filed: August 5, 2004
    Publication date: September 29, 2005
    Inventors: Soichi Yamazaki, Katsuaki Natori, Koji Yamakawa
  • Publication number: 20050186767
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Application
    Filed: April 21, 2005
    Publication date: August 25, 2005
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi
  • Publication number: 20050181559
    Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a bottom electrode film of a capacitor above a semiconductor substrate, forming a dielectric film of the capacitor on the bottom electrode film, forming a top electrode film of the capacitor on the dielectric film, and forming a hydrogen barrier film after forming the top electrode film, the hydrogen barrier film preventing hydrogen from diffusing into the dielectric film, wherein forming the hydrogen barrier film includes forming an oxide film containing silicon and nitriding the oxide film.
    Type: Application
    Filed: June 29, 2004
    Publication date: August 18, 2005
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya
  • Patent number: 6924519
    Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and comprising a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, at least one of the bottom electrode and the top electrode comprising a conductive film selected from a noble metal film and a noble metal oxide film, a metal oxide film having a perovskite structure, provided between the dielectric film and the conductive film, represented by ABO3, and containing a first metal element as a B site element, and a metal film provided between the conductive film and the metal oxide film, and containing a second metal element which is a B site element of a metal oxide having a perovskite structure, a decrease of Gibbs free energy at a time when the second metal element forms an oxide being larger than that at a time when the first metal element forms an oxide.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: August 2, 2005
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AG
    Inventors: Hiroshi Itokawa, Koji Yamakawa, Keitaro Imai, Katsuaki Natori, Bum-ki Moon
  • Publication number: 20050110062
    Abstract: A semiconductor device comprises a semiconductor substrate including a diffusion area, a capacitor provided above the semiconductor substrate and including a lower electrode, a dielectric film, and an upper electrode, a plug provided between the semiconductor substrate and the capacitor and having a lower end connected to the diffusion area and an upper end connected to the lower electrode, and a dummy plug provided between the semiconductor substrate and the capacitor and having a lower end not connected to the diffusion area and an upper end connected to the lower electrode.
    Type: Application
    Filed: October 1, 2004
    Publication date: May 26, 2005
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya
  • Publication number: 20050070043
    Abstract: The present invention provides a method for manufacturing a semiconductor device equipped with a capacitor in which a dielectric film is used, wherein a complex oxide is used as a mask material when the dielectric film is etched.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Osamu Arisumi, Hiroshi Itokawa, Hiroyuki Kanaya, Kazuhiro Tomioka, Keisuke Nakazawa, Yasuyuki Taniguchi, Uli Egger
  • Publication number: 20050070031
    Abstract: There is disclosed a method of manufacturing a semiconductor device, comprising forming an underlying region including an interlevel insulating film on a semiconductor substrate, forming an alumina film on the underlying region, forming a hole in the alumina film, filling the hole with a bottom electrode film, forming a dielectric film on the bottom electrode film, and forming a top electrode film on the dielectric film.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Keitaro Imai, Koji Yamakawa, Hiroshi Itokawa, Katsuaki Natori, Osamu Arisumi, Keisuke Nakazawa, Bum-ki Moon
  • Publication number: 20050051823
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and including a film which contains Pb, Sr, Zr, Ti, Ru and O and a dielectric film which contains Pb, Zr, Ti and O and which is provided on the film containing Pb, Sr, Zr, Ti, Ru and O.
    Type: Application
    Filed: April 28, 2004
    Publication date: March 10, 2005
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Publication number: 20050001251
    Abstract: A semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate, and including a bottom electrode, a top electrode and a dielectric film between the bottom and top electrodes, the bottom electrode including a conductive film selected from a noble metal film and a noble metal oxide film, a metal oxide film having a perovskite structure, provided between the dielectric film and the conductive film, expressed by ABO3, and containing first metal element as B-site element, and a metal film provided between the conductive film and the metal oxide film, and containing second metal element which is B-site element of a metal oxide having a perovskite structure, a decrease of Gibbs free energy when the second metal element forms oxide being larger than that when the first metal element forms oxide, a thickness of the metal oxide film being 5 nm or less.
    Type: Application
    Filed: April 30, 2004
    Publication date: January 6, 2005
    Inventors: Hiroshi Itokawa, Koji Yamakawa, Katsuaki Natori
  • Publication number: 20040217404
    Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and comprising a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, at least one of the bottom electrode and the top electrode comprising a conductive film selected from a noble metal film and a noble metal oxide film, a metal oxide film having a perovskite structure, provided between the dielectric film and the conductive film, represented by ABO3, and containing a first metal element as a B site element, and a metal film provided between the conductive film and the metal oxide film, and containing a second metal element which is a B site element of a metal oxide having a perovskite structure, a decrease of Gibbs free energy at a time when the second metal element forms an oxide being larger than that at a time when the first metal element forms an oxide.
    Type: Application
    Filed: May 2, 2003
    Publication date: November 4, 2004
    Inventors: Hiroshi Itokawa, Koji Yamakawa, Keitaro Imai, Katsuaki Natori, Bum-ki Moon
  • Publication number: 20040206993
    Abstract: A ferrocapacitor device comprising a ferroelectric capacitor structure which includes a bottom electrode 5, a ferroelectric layer 7, and a top electrode 9, formed over a substructure 1. A first Al2O3 cover layer 15 is deposited over the structure by a physical vapour deposition process (such as sputtering), and a second Al2O3 cover layer 17 is deposited over the first Al2O3 cover layer 15 by atomic layer deposition. The first Al2O3 cover layer 15 protects the capacitor structure during the formation of the second Al2O3 cover layer 17, and the second Al2O3 cover layer 17 protects the capacitor structure during back end processes performed on the FeRAM device.
    Type: Application
    Filed: April 17, 2003
    Publication date: October 21, 2004
    Applicants: Infineon Technologies AG, Kabushiki Kaisha Toshiba
    Inventors: Karl Hornik, Haoren Zhuang, Bum Ki Moon, Andreas Hilliger, Katsuaki Natori
  • Publication number: 20040171252
    Abstract: An improved method of reducing contamination in processing of ICs is disclosed. The method includes forming a contamination protection layer on at least the back surface of the substrate. The contamination protection layer comprises a low diffusion factor and can be cleaned efficiently. In one embodiment, the contamination protection layer comprises HCD silicon nitride.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Inventors: Haoren Zhuang, Katsuaki Natori, Gerhard Beitel, Bum-ki Moon, Moto Yabuki, Yoshitaka Tsunashima, Karl Hornik