Abstract: A semiconductor memory device comprises a semiconductor substrate, a plurality of memory cells each comprised of a cell transistor having at least a pair of source and drain regions formed in the semiconductor substrate and a gate electrode formed thereon, a bit line, a bit contact for providing contact between the drain region and the bit line, a capacitor and a storage contact for providing contact between the source region and the capacitor, in which the pair of source and drain regions are disposed in limited areas near the gate electrode and independent form not sharing those in other memory cells.

Abstract: A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor includes respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

Abstract: A method for forming a resist mask pattern by light exposure providing the steps of forming a resist layer on a semiconductor substrate, forming a phase shifter pattern for inverting a phase of exposed light in an upper portion of the resist layer itself or over the surface of the resist layer, exposing the surface of the semiconductor substrate including the phase shifter pattern, and forming a fine mask pattern below the edge of the phase shifter pattern.

Abstract: A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes of a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor is includes of respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

Abstract: A semiconductor memory device is provided which includes a plurality of memory cells, each of which includes: an active region having an MOS transistor formed in the surface portion of a semiconductor substrate; a gate electrode formed on the substrate for the MOS transistor so as to divide the active region into a source-side active region with a storage contact and a drain-side active region with a bit contact, the portion of the active region which is positioned under the gate electrode functioning as a channel region for the MOS transistor; a first impurity-implanted region formed in a portion of the source-side active region so as to overlap with part of the storage contact and the gate electrode, the portion of the source-side active region which overlaps with the first impurity-implanted region functioning as a source region for the MOS transistor; and a second impurity-implanted region formed in a portion of the drain-side active region so as to overlap with at least one part of the bit contact and th

Abstract: An isolator for isolating semiconductor devices, components of an integrated circuit, on a semiconductor substrate, wherein the isolator is delimited by walls of a trench formed on a top surface of the semiconductor substrate, and the trench is filled with a silicon oxide layer deposited by a chemical vapor deposition method. A small ditch created in the middle of a top surface of the silicon oxide layer in the trench is filled with silicon, and at least a top surface of the silicon is thermally oxidized to form another silicon oxide layer.

Abstract: A method of fabricating an insulating gate type field-effect transistor in which a region having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region having a high carrier density, the method comprising the steps of: forming a gate insulating film and a gate electrode on a semiconductor substrate; depositing an insulating thin film on the gate electrode and the gate insulating film to a vertical thickness; and performing from above the insulating thin film, ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness of the insulating thin film so as to form the source/drain region; wherein a horizontal thickness of the insulating thin film on opposite sides of the gate electrode is larger than a sum of a lateral diffusion distance of the source/drain region at the time of the ion implantation and a lateral diffusion distance of the source/drain region after the ion implantation.

Abstract: A semiconductor memory device of a type comprising a plurality of sense amplifiers of differential type arranged in one direction, a pair of bit lines extending outwardly from opposite sides of each of the sense amplifiers, a plurality of word lines extending in a direction intersecting the bit lines, and a memory cell disposed at each of intersecting points between the bit lines and the word lines. The device is characterized in that the memory cells which are connected respectively with the neighboring bit lines are connected with the different word lines. Therefore, not only can the interference noise between each bit-line pair be reduced, but also any possible erroneous operation can be eliminated, thereby increasing the data reading speed.

Abstract: A process for forming a semiconductor device isolation region which comprises:a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon,b) etching the substrate using a resist pattern to form a trench for providing an isolation region,c) forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall of the trench,d) subsequently forming a first polycrystalline silicon film on the substrate including the trench, leaving the first polycrystalline silicon film only on the side walls of the trench by anisotropic etching and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench, ande) further forming a second polycrystalline silicon film over the semiconductor substrate including the trench, leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching and thereafter oxid

Abstract: A semiconductor memory having a plurality of memory cells each including a single capacitor and a single transistor for storing one bit are formed on a semiconductor substrate. Each terminal of the respective transistors of the memory cells are commonly connected to a common wiring portion, and the capacitor of each memory cell is disposed in a trench which is formed by forming a groove-like shape along the outer periphery of the semiconductor substrate for one or two adjacent transistors. The capacitor includes a first insulating film disposed over the inner wall surface of the trench, a first electrode formed entirely or partially on the surface of the first insulating film for being supplied with a predetermined voltage, a second insulating film disposed entirely over the surface of the first electrode, and a second electrode disposed on the second insulating film in an area corresponding to the inner sidewall surface of the trench and connected to the other terminal of the transistor.