Abstract: Provided is a simple light irradiation apparatus capable of performing uniform irradiation even on to a treatment area having a curved surface and capable of suppressing excessive heating caused by light irradiation. The light irradiation apparatus (10) includes a polymer gel layer (3) that covers the treatment area (2) on skin (1), an LED protective layer (6) that closely adheres to the polymer gel layer (3), and a substrate (5) on which LEDs (4) closely adhered to the LED protective layer (6) are arranged thereon. A current control apparatus (8) which lights the LEDs (4) controls irradiation intensity and stops irradiation when. reaching a demanded dose amount.

Abstract: A nitride semiconductor light-emitting element at least includes an underlayer, an n-type contact layer, a light-emitting layer, and a p-type nitride semiconductor layer successively disposed on a substrate. The film thickness ratio R, the ratio of the thickness of the n-type contact layer to the thickness of the underlayer, is 0.8 or less. The number density of V-pits in the surface of the light-emitting layer located on the p-type nitride semiconductor layer side is 1.5×108/cm2 or less. This can provide a nitride semiconductor light-emitting element that can realize improvements in the light emission efficiency at the actual operating temperature and the temperature characteristic and an improvement in the ESD resistance without causing conflict.

Abstract: A nitride semiconductor light-emitting element includes at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer. A multilayer body is provided between the n-type nitride semiconductor layer and the light-emitting layer, having at least one stack of first and second semiconductor layers. The second semiconductor layer has a greater band-gap energy than the first semiconductor layer. The first and second semiconductor layers each have a thickness of more than 10 nm and 30 nm or less. In applications in which luminous efficiency at room temperature is a high priority, the first semiconductor layer has a thickness of more than 10 nm and 30 nm or less, the second semiconductor layer has a thickness of more than 10 nm and 40 nm or less, and the light-emitting layer has V-shaped recesses in cross-sectional view.

Abstract: A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface.

Abstract: A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface.

Abstract: A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.

Abstract: A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.

Abstract: A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a trench groove in the semiconductor substrate by successively processing the oxidation-resistant deposition film, the first dielectric film and the semiconductor substrate by anisotropic etching; forming a second dielectric film to cover at least an inner surface of the trench groove; depositing a third dielectric film in the trench groove so that the thickness of the third dielectric film buried in the trench groove is larger than a depth of the trench groove; planarizing a surface of the third dielectric film and an upper surface of the trench groove; and removing the oxidation-resistant deposition film and the first dielectric film to form the device isolation region, wherein a thermal treatment of the entire substrate is carried out to densify the third dielectric film and to oxidize an interface between the seco

Abstract: A method of fabricating a semiconductor memory device comprises the steps of: (a) forming an interlayer insulating film on a semiconductor substrate, opening a contact hole in said interlayer insulating film, and burying a plug in said contact hole; (b) forming a first insulating film on said interlayer insulating film inclusive of said plug, and forming a trench in said first insulating film above said plug; (c) forming a first conductive film on said first insulating film inclusive of said trench, and etching back said first conductive film by a chemical mechanical polishing method to form a bottom electrode inside said trench; (d) forming a high dielectric film or a ferroelectric film and a second conductive film in this order on said first insulating film inclusive of said bottom electrode; and (e) patterning simultaneously said high dielectric film or ferroelectric film and said second conductive film to form a capacitor insulating film and a top electrode.

Abstract: A method of manufacturing a semiconductor device comprises; forming a device isolation region in a semiconductor substrate; forming at least a first conductivity type impurity region in the semiconductor substrate; and forming on the semiconductor substrate a transistor including a gate insulating film, a gate electrode, source/drain regions and a channel located directly under the gate electrode, wherein the first conductivity type impurity region is formed by the steps of: an ion implantation 1 having a concentration peak at a location deeper than the bottom of the device isolation region; an ion implantation 2 having a concentration peak at a location around the bottom of the device isolation region; an ion implantation 3 having a concentration peak around the junction regions where the source/drain regions are to be formed; and an ion implantation 4 having a concentration peak on the surface or directly under the surface of the region where the channel is to be formed.

Abstract: A semiconductor device comprises a plurality of transistors A semiconductor device comprising a plurality of transistors formed on a semiconductor substrate and a metal interconnection layer connected to at least one of the transistors, wherein the metal interconnection layer is composed of a single layer or multi layers, the single layer or at least one layer of the multi layers being formed of copper or a copper alloy, and is connected to at least one transistor wholly or partially through a barrier layer; and at least one of the transistor is controlled on its threshold voltage by a selective ion implantation after formation of the metal interconnection layer.

Abstract: An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery o

Abstract: The nonvolatile memory cell of this invention includes a floating gate formed of an ultra-thin polycrystalline silicon film. Since the memory cell includes such an ultra-thin floating gate with a smooth surface, problems occurring in the patterning for the floating gate in conventional memory cells can be solved. In addition, the memory cells of the invention are suitable for device integration. Especially when the floating gate is formed of a polycrystalline silicon film, the device characteristics such as writing speed are remarkably improved.

Abstract: A method for rewriting a flash memory wherein a plurality of memory cells each of which comprises a pair of source and drain, a floating gate and a control gate are arranged in matrix in a first conductivity-type well formed in a second conductivity-type deep well formed in the first conductivity-type semiconductor substrate; and in which the floating gate is charged with electrons when the flash memory is written and the floating gate is discharged of the electrons when the flash memory is erased; in which the erasure of the flash memory is operated by applying to the first conductivity-type well a first positive voltage different from the potential of the substrate, applying to the source or the drain a second positive voltage higher than the first positive voltage and applying to the control gate a first negative voltage.

Abstract: The nonvolatile memory cell of this invention includes a floating gate formed of an ultra-thin polycrystalline silicon film. Since the memory cell includes such an ultra-thin floating gate with a smooth surface, problems occurring in the patterning for the floating gate in conventional memory cells can be solved. In addition, the memory cells of the invention are suitable for device integration. Especially when the floating gate is formed of a polycrystalline silicon film, the device characteristics such as writing speed are remarkably improved.

Abstract: In a design rule checking method of the invention, pattern data for forming one layer is divided into two types of pattern data for an A layer and a B layer. Then, A rules to be satisfied by the pattern data for the A layer, B rules to be satisfied by the pattern data for the B layer, and AB rules to be satisfied by a combination of the two types of pattern data for the A and B layers are established. Then, based on the established rules, it is checked to see whether the pattern data for the A layer satisfies the A rules, whether the pattern data for the B layer satisfies the B rules and whether the combination of the two types of pattern data for the A and B layers satisfies the AB rules.

Abstract: A method of fabricating a semiconductor device having a p-type semiconductor substrate and a p-well for memory cells which is formed in the substrate is disclosed. N-type impurities are implanted into a region of the substrate in which the p-well for memory cells is to be formed. Then, the region is selectively and thermally oxidized to form an oxide film on the first region, and the n-type impurities are simultaneously diffused in the substrate. After the oxide film is removed, the p-well is formed within the region of the substrate in which the n-type impurities are diffused.

Abstract: A mask for photolithography having a transparent substrate which allows light having a predetermined wavelength to pass therethrough; an opaque pattern provided on said substrate for inhibiting the light from passing therethrough; and a stepped portion provided adjacent to said opaque pattern on said substrate and having an inclined area, said stepped portion being transparent for allowing the light to pass therethrough, which can be used in a photolithographic system in fabrication of semiconductor devices and the like.

Abstract: Element isolation regions are first formed on a silicon substrate. Active regions other than the isolation regions are formed with an oxide film. Then, a first oxidization prevention layer, a semiconductor layer and a second oxidization prevention layer are formed on the substrate in that order. A resist pattern having a hole in a P-channel MOS transistor formation region is formed. The second oxidization prevention layer in the P-channel MOS transistor formation region is removed and an impurity is ion-implanted using the resist pattern as a mask. After removing the resist pattern, the substrate is thermally treated in the presence of an oxidizer substance to transform an exposed portion of the semiconductor layer into an oxidized semiconductor layer and at the same time to diffuse the implanted impurity in the substrate to thereby form an N-well.

Abstract: A semiconductor memory device which comprises unit memory cells each including two transistors each having a source/drain region and a gate electrode and one capacitor having a capacitor dielectric film, an upper electrode and a lower electrode, the gate electrode of each transistor being connected to a common word line, one source/drain region of each transistor being connected to a bit line and a reversed bit line respectively and the other source/drain region being connected to the upper electrode and the lower electrode respectively, and the bit line, the reversed bit line and the word line being disposed under the lower electrode of the capacitor.