Patents by Inventor Katsumi Mori

Katsumi Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12125905
    Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: October 22, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Kaya, Katsumi Eikyu, Akihiro Shimomura, Hiroshi Yanagigawa, Kazuhisa Mori
  • Patent number: 10930635
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 23, 2021
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20200258877
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 10679979
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 9, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20190035776
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 10121741
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 6, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9978737
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 22, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9953922
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 24, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9926899
    Abstract: A fuel-filter abnormality detection device is used for a subject filter provided in a fuel supply device of an engine to filtrate a fuel. The fuel-filter abnormality detection device includes a first filter attachable downstream of the subject filter in fuel flow. A filtration capacity of the first filter is smaller than a filtration capacity of the subject filter, and the first filter traps a foreign matter on a downstream side of the subject filter to cause a change in fuel pressure indicating an abnormality of the subject filter. The fuel-filter abnormality detection device may include a bypass passage through which the fuel bypasses the first filter, a bypass control valve configured to allow the fuel to flow through the bypass passage when the abnormality of the subject filter is detected, and a second filter filtrating the fuel flowing through the bypass passage.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: March 27, 2018
    Assignee: KYOSAN DENKI CO., LTD.
    Inventors: Takafumi Kato, Toshiyuki Yonemoto, Katsumi Mori
  • Publication number: 20170162498
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Publication number: 20170162499
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Publication number: 20160358901
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 9455223
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: September 27, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9297376
    Abstract: A supply pump includes a housing, a tappet, a guide groove, and a stopper pin. The housing includes a cylindrical sliding wall. The tappet is configured to be reciprocated along the sliding wall. The guide groove is provided for one of the housing and the tappet. One end of the guide groove includes a tapered surface. The stopper pin is provided for the other one of the housing and the tappet. The stopper pin is fitted into the guide groove to stop rotation of the tappet relative to the housing. When the tappet is displaced abnormally in an upper direction, the tapered surface is pressed on an end of the stopper pin to be engaged with the stopper pin.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: March 29, 2016
    Assignee: DENSO CORPORATION
    Inventors: Takaharu Sakoh, Katsumi Mori, Nao Ogasawara
  • Publication number: 20150360152
    Abstract: A fuel-filter abnormality detection device is used for a subject filter provided in a fuel supply device of an engine to filtrate a fuel. The fuel-filter abnormality detection device includes a first filter attachable downstream of the subject filter in fuel flow. A filtration capacity of the first filter is smaller than a filtration capacity of the subject filter, and the first filter traps a foreign matter on a downstream side of the subject filter to cause a change in fuel pressure indicating an abnormality of the subject filter. The fuel-filter abnormality detection device may include a bypass passage through which the fuel bypasses the first filter, a bypass control valve configured to allow the fuel to flow through the bypass passage when the abnormality of the subject filter is detected, and a second filter filtrating the fuel flowing through the bypass passage.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 17, 2015
    Inventors: Takafumi KATO, Toshiyuki YONEMOTO, Katsumi MORI
  • Patent number: 9151290
    Abstract: A cylinder body includes a cylinder hole and a discharge flow passage. The cylinder hole receives a plunger and forms a pressurizing chamber in one axial end portion thereof. The discharge flow passage is connected to the pressurizing chamber and is adapted to guide and discharge the pressurized fuel from the pressurizing chamber to an outside of the housing. A connection opening of the discharge flow passage is formed in a hole wall of the cylinder hole. A pressure is applied to a predetermined prestressing subject area in the hole wall of the cylinder hole and a passage wall of the discharge flow passage through autofrettage to generate a residual compression stress in the predetermined prestressing subject area and thereby to form a prestressed area of a final product. The prestressing subject area includes an inner peripheral edge of the connection opening.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: October 6, 2015
    Assignee: DENSO CORPORATION
    Inventors: Tetsuya Yoshimura, Katsumi Mori, Kenichi Niinuma
  • Publication number: 20150155232
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Application
    Filed: February 4, 2015
    Publication date: June 4, 2015
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 8984466
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20140110853
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: Seiko Epson Corporation
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 8637950
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 28, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya