Patents by Inventor Katsumi Mori

Katsumi Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6501778
    Abstract: The present invention aims at providing a light source for a semiconductor laser beam scanner having high resolution in scanning and a high degree of mounting freedom, and suitable for emitting a laser beam from the surface. Therefore, a surface emission type semiconductor laser includes at least a first mirror 102, an active layer 103, a current narrowing layer 113, a contact layer 106, and a second mirror 111, which are formed on a semiconductor substrate 101; wherein the current narrowing layer 113 is made of a stripe AlAs layer 105, and an Al oxide layer 108 formed to surround the AlAs layer 105; the region of the contact layer 106, which overlaps the Al oxide layer, is formed in a comb shape 109, and independent contact electrodes 110 are respectively formed on the upper surfaces of the teeth of the comb shape 109 of the contact layer.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: December 31, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Takayuki Kondo, Takeo Kaneko, Katsumi Mori
  • Publication number: 20020192092
    Abstract: A fuel injection pump has a drive shaft. A cam rotates together with the drive shaft. A plurality of plungers, slidably supported by a pump housing and driven by the cam, reciprocate in accordance with rotation of the cam to pressurize the fuel introduced in a fuel pressurizing chamber. The pressurized fuel is fed to an accumulator via a fuel feed passage formed in the pump housing. A pipe joint portion is integrally formed with the pump housing and is directly connected to a piping member of the accumulator.
    Type: Application
    Filed: June 18, 2002
    Publication date: December 19, 2002
    Inventor: Katsumi Mori
  • Patent number: 6475879
    Abstract: A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: November 5, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Katsumi Mori
  • Publication number: 20020148008
    Abstract: The present invention provides an isolated gene which regulates the dormancy of wheat seed, an antisense DNA to said gene, an isolated protein having activity which alters the degree of dormancy of wheat seed, a recombinant vector containing the gene, a transformant containing the vector; and a method for producing the protein.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 10, 2002
    Inventors: Shingo Nakamura, Katsumi Mori
  • Publication number: 20020127469
    Abstract: An alkaline battery constructed of a cathode can and an anode cup in such a way that an open end of the cathode can is sealed by the anode cup, with a gasket interposed between them, characterized in that the open end of the anode cup is folded back in U-shape along its periphery and the fold is tightened for hermetic sealing by the internal periphery of the open end of the cathode can, with the gasket interposed between them, the anode cup has a higher hydrogen over potential material coating layer formed in a limited region on the inside thereof excluding the bottom of the U-shaped fold and the outer periphery of the fold, the cathode can contains the cathode active material and silver-nickelite (AgNiO2), the anode cup contains the anode mix which is mercury-free zinc or zinc alloy powder as the anode active material.
    Type: Application
    Filed: September 6, 2001
    Publication date: September 12, 2002
    Inventors: Katsumi Mori, Takumi Ohhara, Kenji Sato
  • Patent number: 6437455
    Abstract: A semiconductor memory device comprising first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect a gate of a driver transistor to a gate of a load transistor. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and have a refractory metal nitride layer. The first and second drain-drain connecting layers respectively connect a drain of the driver transistor to a drain of the load transistor. The first and second drain-gate connecting layers are formed over a second interlayer dielectric, and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer, and the second drain-drain connecting layer to the first gate-gate connecting layer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: August 20, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20020104514
    Abstract: A camshaft has a cam having a circular profile. A cam-ring is rotatably arranged on a radial outside of the cam. The cam-ring orbits around the cam. The cam-ring has a metal bush on an inner surface thereon. The cam-ring rotates relative to the cam, but is prevented from a rotation itself. The cam has a groove inclined with respect to a rotating axis of the cam. The groove has openings on both axial ends of the cam. The groove introduces fuel as a lubricant into a gap between the cam and the metal bush. The fuel introduced into the gap improves a lubricity and prevents a sticking.
    Type: Application
    Filed: January 30, 2002
    Publication date: August 8, 2002
    Inventors: Katsumi Mori, Katsunori Furuta
  • Patent number: 6417083
    Abstract: Certain embodiments provide a manufacturing method for a semiconductor device, in which an organic antireflection film can be etched while a resist layer maintains dimensions thereof. The method includes forming an oxide layer 24 on a p-type silicon substrate 10, and forming a polysilicon layer 26 on the oxide layer 24. An organic antireflection film 30 is formed on the polysilicon layer 26, and a resist layer R having a predetermined pattern is formed on a surface of the organic antireflection film 30. The method as includes etching the organic antireflection film 30 by using the resist layer R, in which an etching gas includes at least one of an oxygen-based gas and a chlorine-based gas, and forming a gate electrode by etching the polysilicon layer 26 with a predetermined pattern.
    Type: Grant
    Filed: November 11, 1999
    Date of Patent: July 9, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Katsumi Mori
  • Patent number: 6404023
    Abstract: A semiconductor device comprising a peripheral circuit portion and a memory cell portion including a plurality of memory cells. Each memory cell has first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect the gates of driver transistors to the gates of load transistors. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and respectively connect the drains of driver transistors to the drains of load transistors. The first and second drain-gate connecting layers are formed over a second interlayer dielectric and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer and the second drain-drain connecting layer to the first gate-gate connecting layer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: June 11, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20020048757
    Abstract: The present invention provides a simple and quick method for determining the nucleotide sequence of the mitochondrial 21S ribosomal RNA gene of Saccharomyces cerevisiae by gene amplification technique, and a method for classifying Saccharomyces cerevisiae strains using the same nucleotide sequence.
    Type: Application
    Filed: March 2, 2001
    Publication date: April 25, 2002
    Inventors: Katsumi Mori, Takuma Gamou
  • Patent number: 6364641
    Abstract: In a fuel injection pump, flat sections are provided around a connecting segment located between an inner wall surface of a pump housing defining a fuel pressurizing chamber and an inner wall surface of a fuel intake passage as well as a connecting segment located between the wall surface of the pump housing and an inner wall surface of a fuel discharge passage 15 to spread stresses concentrated in upper and lower intersecting points of each connecting segment over an entire periphery of the connecting segment. As a result, the strength of the fuel injection pump is improved to allow use of higher fuel injection pressures. Furthermore, the strength of the fuel injection pump is improved without increasing a wall thickness of the pump housing, so that a size of the fuel injection pump is not increased.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: April 2, 2002
    Assignee: Denso Corporation
    Inventor: Katsumi Mori
  • Patent number: 6357415
    Abstract: A fuel shut-off safety device is mounted in a fuel injection system for an internal combustion engine. The fuel shut-off safety device includes a cylindrical body having a fuel passage and a valve seat, a piston disposed to slide in the fuel passage, a valve body to shut off the fuel passage when it is seated on the valve seat, a center bore connected to the fuel inlet, and an aperture connecting the center bore and the fuel passage, and a compression coil spring for biasing the piston to unseat the valve body from the valve seat.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: March 19, 2002
    Assignee: Denso Corporation
    Inventor: Katsumi Mori
  • Publication number: 20020014221
    Abstract: A pressure limiter is connected fluid-tight between a common rail having an accumulator for storing high-pressure fuel delivered from a high-pressure fuel feed pump and a relief line. In a valve body of this pressure limiter, a damper chamber is provided on the downstream side of the sliding bore, for housing a large diameter portion of the piston and holding fuel, to thereby control the downward speed of the ball valve and the piston when the ball valve and the piston are shifted to the valve closing side by the force of the spring. Thus it becomes possible to prolong the downward-moving time of the ball valve and the piston.
    Type: Application
    Filed: June 26, 2001
    Publication date: February 7, 2002
    Inventor: Katsumi Mori
  • Publication number: 20010049179
    Abstract: A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.
    Type: Application
    Filed: January 17, 2001
    Publication date: December 6, 2001
    Inventor: Katsumi Mori
  • Publication number: 20010042921
    Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
    Type: Application
    Filed: March 15, 2001
    Publication date: November 22, 2001
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20010039647
    Abstract: A method is provided for generating mask data that is used for forming dummy convex regions in a specified pattern in a trench isolation region in a semiconductor device. Mask and computer readable recording medium are also provided. The method includes the steps of (a) setting a restriction region pattern 262 that defines a restriction region 40 in a semiconductor substrate, (b) setting dummy patterns 310 that define dummy convex regions 32, and (c) mixing the restriction region pattern 262 and the dummy patterns 310, wherein the dummy patterns 310 that at least partially overlap the restriction region pattern 262 are entirely excluded.
    Type: Application
    Filed: March 14, 2001
    Publication date: November 8, 2001
    Inventors: Katsumi Mori, Yoshikazu Kasuya, Kei Kawahara
  • Publication number: 20010030372
    Abstract: A semiconductor memory device comprising first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect a gate of a driver transistor to a gate of a load transistor. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and have a refractory metal nitride layer. The first and second drain-drain connecting layers respectively connect a drain of the driver transistor to a drain of the load transistor. The first and second drain-gate connecting layers are formed over a second interlayer dielectric, and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer, and the second drain-drain connecting layer to the first gate-gate connecting layer.
    Type: Application
    Filed: January 12, 2001
    Publication date: October 18, 2001
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20010026992
    Abstract: A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation region 24 define first virtual linear lines L1 that extend in a direction traversing the row direction and second virtual linear lines L2 that extend in a direction traversing the column direction. The first virtual linear lines L1 and the row direction define an angle of 2-40 degree, and the second virtual linear lines L2 and the column direction define an angle of 2-40 degree. The dummy convex regions 32 are disposed on the first virtual linear lines L1 and the second virtual linear lines L2.
    Type: Application
    Filed: January 17, 2001
    Publication date: October 4, 2001
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20010017394
    Abstract: A semiconductor wafer 10 has a chip region 20 and a non-chip region 22. Dummy trench isolation regions 40 are formed in at least a part of the non-chip region 22 of the semiconductor wafer 10. The dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22. A method is also provided for processing a semiconductor wafer 10 having a chip region 20 and a non-chip region 22. The method includes a process for forming trench isolation regions in the semiconductor wafer 10. The process includes the steps of forming dummy trench isolation regions 40 in at least a part of the non-chip region 22 of the semiconductor wafer 10, wherein the dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22.
    Type: Application
    Filed: February 2, 2001
    Publication date: August 30, 2001
    Inventors: Katsumi Mori, Kenji Kojima
  • Publication number: 20010015200
    Abstract: In a fuel injection pump, a helical gear is attached to an end of a camshaft and rotatable with the camshaft. The camshaft is biased in one axial direction thereof by a driving force that the helical gear receives from an engine crankshaft. A disk is provided in a position of the camshaft extending forward from a cam to the direction in which the camshaft is biased. An axial movement of the disk is restricted via a washer by an end of a bearing cover. The disk is formed in the same axis to a portion of the camshaft that is held by a journal bearing. An outer diameter of the disk is larger than that of the cam. An area where the disk and the washer are in sliding contact with each other is relatively large and the sliding regions thereof are constant so that hammer noises are prevented and frictional wear thereof are limited.
    Type: Application
    Filed: February 5, 2001
    Publication date: August 23, 2001
    Inventor: Katsumi Mori