Abstract: A method for manufacturing a semiconductor device that maintains good embedding property of plug metal, and expands the short margin of upper wiring layers to be connected to plugs, may include enlarging an end region 18 of a hole 12, such that embedding of a barrier metal 13 and a plug metal 14 in the hole 12 that is given a high aspect ratio is facilitated. Next, a planarization step is conducted against deposited surfaces of the plug metal 14 by a chemical mechanical polishing (CMP) process. In this step, a part of the interlayer dielectric layer 11 is removed together with an unnecessary portion of the plug metal 14 to a level where the end region (having a diameter d2) that is greater than a practical diameter d1 of the hole 12 disappears. Then, an upper wiring layer 15 is patterned, using a lithography technique, on the planarized interlayer dielectric layer 11 having an exposed portion of the plug metal 14 that has the practical diameter of the hole.

Abstract: A body member of a common rail is formed with an accumulator chamber hole that is a through hole providing first and second openings on both ends of the body member. A sealing plug is inserted into the accumulator chamber hole from the second opening and is press-fitted into a reduced diameter part of the accumulator chamber hole so far as the sealing plug contacts a contacting part near the first opening. Thus, the sealing plug closes the first opening. When high-pressure fuel is accumulated in the accumulator chamber, the sealing plug is pressed against the contacting part. Accordingly, the sealing plug and the contacting part are adhered with each other tightly. Therefore, leak of the fuel is surely prevented.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a specified pitch. A first insulation layer 33 is embedded between adjacent ones of the fuses 20. A second insulation layer 39 is formed on the first insulation layer 33. The first insulation layer 33 and the second insulation layer 39 are formed such that their interface 42 is generally at the same level as the top surface of the fuses 20. As a result, the fuses may be reliably fused without generating cracks in the interface 42 at the time of fusing the fuses.

Abstract: An oil supply means is provided to supply the center portion of a rotating part of an Oldham coupling with oil. The oil spreads from the center of rotation to the outside of the Oldham coupling and makes it possible to prevent the Oldham coupling from wearing. A recess is also provided to direct the oil supplied from an engine to the inward portion of the Oldham coupling. Accordingly, the oil is supplied all over an Oldham projection so that it is possible to prevent the frictional wearing of the Oldham projection disposed inside the Oldham coupling.

Abstract: A method, for fabricating a semiconductor device including a memory region and a logic circuit region including a periphery circuit, includes: forming sidewall-like control gates on both side surfaces of a first conductive layer at least in a memory region with an ONO film interposed therebetween, respectively; patterning a first conductive layer in a logic circuit region and thereby forming a gate electrode of a MOS transistor; forming a second insulating layer above the control gates; applying anisotropic etching to the second insulating layer, and thereby at least partially exposing the control gates; and on the exposed surfaces of the control gates, forming a silicide layer.

Abstract: A camshaft has a cam having a circular profile. A cam-ring is rotatably arranged on a radial outside of the cam. The cam-ring orbits around the cam. The cam-ring has a metal bush on an inner surface thereon. The cam-ring rotates relative to the cam, but is prevented from a rotation itself. The cam has a groove inclined with respect to a rotating axis of the cam. The groove has openings on both axial ends of the cam. The groove introduces fuel as a lubricant into a gap between the cam and the metal bush. The fuel introduced into the gap improves a lubricity and prevents a sticking.

Abstract: A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation region 24 define first virtual linear lines L1 that extend in a direction traversing the row direction and second virtual linear lines L2 that extend in a direction traversing the column direction. The first virtual linear lines L1 and the row direction define an angle of 2-40 degree, and the second virtual linear lines L2 and the column direction define an angle of 2-40 degree. The dummy convex regions 32 are disposed on the first virtual linear lines L1 and the second virtual linear lines L2.

Abstract: In a fuel injection pump, a casing fixed to a housing has a pump room and a filter room mostly separated from but partly communicating with the pump room. A feed pump is constituted by the pump room where a feed pump mechanism is connected to an axial end of the drive shaft. A filter element is accommodated in the filter room. A casing cover easily attachable and detachable to the casing has a fuel inlet port through which fuel is sucked to the filter room and, then, flows via the filter element into the pump room where the fuel is pressurized according to rotation of the drive shaft. Accordingly, foreign material contained in fuel is eliminated before entering the pump room. Further, fuel flow area of the fuel element is larger than that of the fuel inlet port, resulting in less pressure loss of fuel passing through the filter element even if mesh size of filter element is smaller.

Abstract: A body member of a common rail is formed with an accumulator chamber hole that is a through hole providing first and second openings on both ends of the body member. A sealing plug is inserted into the accumulator chamber hole from the second opening and is press-fitted into a reduced diameter part of the accumulator chamber hole so far as the sealing plug contacts a contacting part near the first opening. Thus, the sealing plug closes the first opening. When high-pressure fuel is accumulated in the accumulator chamber, the sealing plug is pressed against the contacting part. Accordingly, the sealing plug and the contacting part are adhered with each other tightly. Therefore, leak of the fuel is surely prevented.

Abstract: A method is provided for generating mask data that is used for forming dummy convex regions in a specified pattern in a trench isolation region in a semiconductor device. Mask and computer readable recording medium are also provided. The method includes the steps of (a) setting a restriction region pattern 262 that defines a restriction region 40 in a semiconductor substrate, (b) setting dummy patterns 310 that define dummy convex regions 32, and (c) mixing the restriction region pattern 262 and the dummy patterns 310, wherein the dummy patterns 310 that at least partially overlap the restriction region pattern 262 are entirely excluded.

Abstract: Certain embodiments provide a method for fabricating a semiconductor device in which a conductive layer containing silicon can be etched in a predetermined shape without adversely affecting a gate insulating film. A method for fabricating a semiconductor device in accordance with the present invention includes forming an oxide film 24 on a p-type silicon substrate 10 and forming a polysilicon layer 26 on the oxide film 24. A stopper layer 28 is formed on the surface of the polysilicon layer 26 and an organic antireflection coating 30 is formed on the surface of the stopper layer 28. A resist layer R is formed on the surface of the organic antireflection coating 30. The method also includes etching the organic antireflection coating 30 using the resist layer R as a mask and etching the stopper layer 28. The polysilicon layer 26 is also etched in a predetermined pattern to form a gate electrode.

Abstract: A pressure limiter is connected fluid-tight between a common rail having an accumulator for storing high-pressure fuel delivered from a high-pressure fuel feed pump and a relief line. In a valve body of this pressure limiter, a damper chamber is provided on the downstream side of the sliding bore, for housing a large diameter portion of the piston and holding fuel, to thereby control the downward speed of the ball valve and the piston when the ball valve and the piston are shifted to the valve closing side by the force of the spring. Thus it becomes possible to prolong the downward-moving time of the ball valve and the piston.

Abstract: A semiconductor device 100 includes wiring layers 12 disposed in a specified pattern on a base 10, and an interlayer dielectric layer 20 that covers the wiring layers 12. The interlayer dielectric layer 20 includes a stress relieving dielectric layer 22 disposed in a specified pattern on the base 10, and a planarization dielectric layer 26 that covers the wiring layers 12 and the stress relieving dielectric layers 22, and is formed from a liquid dielectric member. The interlayer dielectric layer 20 may further include a base dielectric layer 24 and a cap dielectric layer 28.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a specified pitch. A first insulation layer 33 is embedded between adjacent ones of the fuses 20. A second insulation layer 39 is formed on the first insulation layer 33. The first insulation layer 33 and the second insulation layer 39 are formed such that their interface 42 is generally at the same level as the top surface of the fuses 20. As a result, the fuses may be reliably fused without generating cracks in the interface 42 at the time of fusing the fuses.

Abstract: A method for generating mask data that is used for a method of manufacturing semiconductor devices is provided. The semiconductor device includes wiring layers disposed in a specified pattern on a base and stress relieving layers disposed in a specified pattern over the base. The method for generating mask data comprises a step of forming resized patterns 130 by resizing wiring layer patterns 120 with a positive (+) resizing amount, a step of deleting, among the resized patterns 130, resized patterns having portions that mutually overlap, and a step of forming stress relieving layer patterns having a specified width outside the resized patterns.

Abstract: A semiconductor device 100 includes wiring layers 12 disposed in a specified pattern on a base 10, and an interlayer dielectric layer 20 that covers the wiring layers 12. The interlayer dielectric layer 20 includes a stress relieving dielectric layer 22 disposed in a specified pattern on the base 10, and a planarization dielectric layer 26 that covers the wiring layers 12 and the stress relieving dielectric layers 22, and is formed from a liquid dielectric member. The interlayer dielectric layer 20 may further include a base dielectric layer 24 and a cap dielectric layer 28.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a pitch X, and an insulation layer 36 having a specified film thickness covers upper portions of the fuses 20. The fuses 20 may have a width W and a film thickness T that have a relation indicated by the following equation: T≧0.4/W. Furthermore, the width W of the fuse 20 may be 3 &mgr;m or less, and may be less than 1/2 of the pitch X of the fuses 20. Also, the film thickness of the fuse 20 may be 0.7 &mgr;m or less.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are formed on a first insulation layer 36 and arranged at a specified pitch. Side surfaces and top surfaces of the fuses 20 are covered by a second insulation layer 19.

Abstract: A semiconductor wafer 10 has a chip region 20 and a non-chip region 22. Dummy trench isolation regions 40 are formed in at least a part of the non-chip region 22 of the semiconductor wafer 10. The dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22. A method is also provided for processing a semiconductor wafer 10 having a chip region 20 and a non-chip region 22. The method includes a process for forming trench isolation regions in the semiconductor wafer 10. The process includes the steps of forming dummy trench isolation regions 40 in at least a part of the non-chip region 22 of the semiconductor wafer 10, wherein the dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22.

Abstract: A method for manufacturing a semiconductor device that maintains good embedding property of plug metal, and expands the short margin of upper wiring layers to be connected to plugs, may include enlarging an end region 18 of a hole 12, such that embedding of a barrier metal 13 and a plug metal 14 in the hole 12 that is given a high aspect ratio is facilitated. Next, a planarization step is conducted against deposited surfaces of the plug metal 14 by a chemical mechanical polishing (CMP) process. In this step, a part of the interlayer dielectric layer 11 is removed together with an unnecessary portion of the plug metal 14 to a level where the end region (having a diameter d2) that is greater than a practical diameter d1 of the hole 12 disappears. Then, an upper wiring layer 15 is patterned, using a lithography technique, on the planarized interlayer dielectric layer 11 having an exposed portion of the plug metal 14 that has the practical diameter of the hole.