Abstract: Valve device is provided with poppet valve for opening and closing flow path. Thread part is formed on shaft of this poppet valve, and driving gear is screwed into this thread part. Driving gear is rotated via pinion by motor, and thereby the poppet valve is moved to advance and retreat so as to control opening and closing of the flow path. Driving gear is provided so as to be able to advance and retreat in the axial direction of the pinion and the axial direction of the poppet valve while remaining engaged with pinion, and is normally held at a predetermined non-operating position by spring (biasing means). With this, even when the poppet valve is seated on the valve seat and has stopped moving, the driving gear moves, when further rotated, against the biasing force of spring from the non-operating position in the axial direction, and absorbs an impact that is applied to the driving means or the like. Damage of the driving means and the like due to the impact load can be prevented.

Abstract: An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer (18) is provided below an N type drift layer (1) in the transistor region. A P type collector layer (19) is provided below the first N type buffer layer (18). A second N type buffer layer (20) is provided below the N type drift layer (1) in the termination region. A collector electrode (21) is directly connected to the P type collector layer (19) and the second N type buffer layer (20). An impurity concentration of the second N type buffer layer (20) decreases as a distance from the collector electrode (21) decreases. The second N type buffer layer (20) does not form any ohmic contact with the collector electrode (21).

Abstract: A p-type anode layer (2) is provided on an upper surface of an n-type drift layer (1). An n-type cathode layer (3) is provided on a lower surface of the n?-type drift layer (1). An n-type buffer layer (4) is provided between the n?-type drift layer (1) and the n-type cathode layer (3). A peak impurity concentration in the n-type buffer layer (4) is higher than that in the n?-type drift layer (1) and lower than that in the n-type cathode layer (3). A gradient of carrier concentration at a connection between the n?-type drift layer (1) and the n-type buffer layer (4) is 20 to 2000 cm?4.

Abstract: An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate.

Abstract: A p-type anode layer (2) provided on an n-type drift layer (1) in the active region. A p-type diffusion layer (3) is provided on the n-type drift layer (1) in a termination region outside the active region. An oxide film (4) covers an outer periphery of the p-type anode layer (2). An anode electrode (5) is connected to a portion of the p-type anode layer (2) not covered with the oxide film (4). An n+-type cathode layer (7) is provided below the n-type drift layer (1). A cathode electrode (8) is connected to the n+-type cathode layer (7). An area of a portion of the p-type anode layer (2) covered with the oxide film (4) is 5 to 30% of a total area of the p-type anode layer (2).

Abstract: An insulating film (2) is formed on a main surface of a semiconductor substrate (1) that includes an active region and a termination region. The insulating film (2) in the active region is etched to form an opening (3). The insulating film (2) is used as a mask and an impurity is implanted into the semiconductor substrate (1) in a direction tilted by 20° or more from a direction normal to the main surface of the semiconductor substrate (1) while rotating the semiconductor substrate (1) to form a diffusion layer (7) in the active region. The diffusion layer (7) extends wider than the opening (3) up to below the insulating film (2) on the termination region side.

Abstract: A drift region has a first conductivity type. A well region is at least partially included in an interface area, has an end portion between the interface area and an edge termination area, and has a second conductivity type. An extension region extends outward from the well region, is shallower than the well region, and has the second conductivity type. A plurality of field-limiting rings are provided outside the extension region in the edge termination area. Each of the field-limiting rings together with the drift region located on the inner side forms a unit structure. The field-limiting ring located closer to the outside has a lower proportion of a width to a width of the unit structure. The unit structure located closer to the outside has a lower average dose.

Abstract: A semiconductor substrate includes a drift region and a collector region. The drift region is provided across an active area, an interface area, and an edge termination area. The collector region is provided only in the active area and forms part of a second surface. An emitter electrode is provided in the active area and contacts a first surface of the semiconductor substrate. A collector electrode is provided on the second surface of the semiconductor substrate and contacts the collector region.

Abstract: The present invention provides a method for producing a hollow engine valve, with which the production process can be simplified and the processing precision can be improved. To this end, the present invention provides a method for producing a hollow engine valve (1) which is provided with a valve main body (10) in which a hollow hole (10c) is formed along a valve umbrella part (10a) and a hollow shaft part (10b), wherein a solid round bar (11) forming the material of the valve main body (10) is molded to a semi-finished article (12) by means of a single hot-forging process, the semi-finished article (12) is subjected to rotary swaging whereby the semi-finished article (12) is molded into a semi-finished article (13), the semi-finished article (13) is subjected to necking whereby the semi-finished article (13) is molded into the valve main body (10), and a shaft end sealing member (20) is joined to the end part of the hollow shaft part (10b) of the valve main body (10).

Abstract: A semiconductor substrate has a first surface and a second surface. A gate electrode has a part buried in a first trench. A capacitor electrode has a part buried in a second trench. An interlayer insulating film is provided on the second surface and having a first contact hole and a second contact hole. A first main electrode is provided on the first surface. A second main electrode contacts the second surface through the first contact hole and contacts the capacitor electrode through the second contact hole. The first and second trenches cross a first range of the second surface. The first and second contact holes are located only in the first range and a second range respectively of the second surface.

Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.

Abstract: The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [?m], and the number of the plurality of units is num, following relationships are satisfied. N?(M×BV)?, M=104 to 105, ?=0.55 to 1.95, SandL×num×Ecri?2×?×BV, Ecri=2.0 to 3.0×105 [V/cm], ?=100 to 101. Widths of the P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.

Abstract: A magnetic resonance imaging (MRI) system includes at least one controller configured to first acquire at least MRI locator image data for different portions of patient anatomy at each of different imaging stations for a defined multi-station locator sequence. An operator may interface with a respectively corresponding displayed locator image for each imaging station to set diagnostic scan sequence parameters for subsequent diagnostic MRI scans of corresponding portions of patient anatomy. Diagnostic MRI scan data is automatically acquired at each of the imaging stations in a multi-station diagnostic scan sequence that, if desired, can be seamlessly continued without operator interruption once begun.

Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.

Abstract: A p-type anode layer (2) is provided on an upper surface of an n-type drift layer (1). An n-type cathode layer (3) is provided on a lower surface of the n?-type drift layer (1). An n-type buffer layer (4) is provided between the n?-type drift layer (1) and the n-type cathode layer (3). A peak impurity concentration in the n-type buffer layer (4) is higher than that in the n?-type drift layer (1) and lower than that in the n-type cathode layer (3). A gradient of carrier concentration at a connection between the n?-type drift layer (1) and the n-type buffer layer (4) is 20 to 2000 cm?4.

Abstract: A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.

Abstract: A magnetic resonance imaging (MRI) system includes at least one controller configured to first acquire at least MRI locator image data for different portions of patient anatomy at each of different imaging stations for a defined multi-station locator sequence. An operator may interface with a respectively corresponding displayed locator image for each imaging station to set diagnostic scan sequence parameters for subsequent diagnostic MRI scans of corresponding portions of patient anatomy. Diagnostic MRI scan data is automatically acquired at each of the imaging stations in a multi-station diagnostic scan sequence that, if desired, can be seamlessly continued without operator interruption once begun.

Abstract: The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers (12a˜120 are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers (12a˜120 respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [?m], and the number of the plurality of units is num, following relationships are satisfied. N?(M×BV)?, M=104 to 105, ?=0.55 to 1.95, SandL×num×Ecri?2×?×BV, Ecri=2.0 to 3.0×105 [V/cm], ?=100 to 101. Widths of the P-type ring layers (12a˜12f) of the plurality of units linearly decrease toward an outside of the termination region.

Abstract: An insulating film (2) is formed on a main surface of a semiconductor substrate (1) that includes an active region and a termination region. The insulating film (2) in the active region is etched to form an opening (3). The insulating film (2) is used as a mask and an impurity is implanted into the semiconductor substrate (1) in a direction tilted by 20° or more from a direction normal to the main surface of the semiconductor substrate (1) while rotating the semiconductor substrate (1) to form a diffusion layer (7) in the active region. The diffusion layer (7) extends wider than the opening (3) up to below the insulating film (2) on the termination region side.

Abstract: An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer (18) is provided below an N type drift layer (1) in the transistor region. A P type collector layer (19) is provided below the first N type buffer layer (18). A second N type buffer layer (20) is provided below the N type drift layer (1) in the termination region. A collector electrode (21) is directly connected to the P type collector layer (19) and the second N type buffer layer (20). An impurity concentration of the second N type buffer layer (20) decreases as a distance from the collector electrode (21) decreases. The second N type buffer layer (20) does not form any ohmic contact with the collector electrode (21).