Patents by Inventor Katsuya Ito
Katsuya Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120183761Abstract: The invention provides a polyester film for the protection of a back surface of a solar cell which, when applied to a silicon thin film solar cell, exhibits excellent durability even under high-temperature and high-humidity conditions and long term thermal stability. The polyester film (a) contains a polyester, as a main constituent, obtained by polymerization using a polycondensation catalyst containing aluminum and/or its compound as well as a phosphorus compound having an aromatic group in the molecule; (b) has a whiteness degree of 50 or higher; (c) contains 3 to 50% by mass of fine particles with a mean particle diameter of 0.1 to 3 ?m; and (d) has an acid value from not lower than 1 (eq/ton) and not higher than 30 (eq/ton).Type: ApplicationFiled: August 30, 2010Publication date: July 19, 2012Applicant: TOYO BOSEKI KABUSHIKI KAISHAInventors: Shiro Hamamoto, Yoshitomo Ikehata, Katsuya Ito, Jun Inagaki
-
Patent number: 7939174Abstract: A film roll of a heat-shrinkable polyester film characterized in that the heat-shrinkable polyester film meets the following requirements (1) and (2). (1) When samples are cut off therefrom at an almost equal interval along the longitudinal direction, and immersed in hot water at 85° C. for 10 seconds, subsequently in water at 25° C. and withdrawn, heat-shrinkage percentages in the maximum shrinkage direction of all the samples are 20% or more. (2) When raw polymers used for production of the film above comprises of a major constitutional unit and one or more sub constitutional units different therefrom; and the content of the primary sub constitutional unit is determined, the content of the primary sub constitutional unit in each sample is more than 7 mole % in 100% of all constitutional units, and when an average of the contents of the primary sub constitutional unit is calculated, the contents thereof of all the samples fall within a range of ±2 mole % relative to the average.Type: GrantFiled: June 23, 2005Date of Patent: May 10, 2011Assignee: Toyo Boseki Kabushiki KaishaInventors: Satoshi Hayakawa, Norimi Tabota, Yoshinori Takegawa, Katsuya Ito, Shigeru Komeda, Katsuhiko Nose
-
Patent number: 7749584Abstract: In heat-shrinkable polyester films, the content of 1,4-cyclohexane dimethanol is 10 to 50% by mole based on the polyhydric alcohol component and that the heat shrinkage factors of a 10 cm square sample of the films in (A) hot water of 75° C., (B) hot water of 85° C., and (C) hot water of 95° C. are 30 to 40%, 50 to 60%, and 65 to 77%, respectively. The films can be produced by drawing under specified conditions.Type: GrantFiled: July 10, 2002Date of Patent: July 6, 2010Assignee: Toyo Boseki Kabushiki KaishaInventors: Satoshi Hayakawa, Norimi Tabota, Yoshinori Takegawa, Katsuya Ito, Shigeru Komeda, Katsuhiko Nose
-
Patent number: 7733632Abstract: A casing includes a first casing member and a second casing member. The first casing member is provided on a side with a fuse module mounting section having a side opening. The second casing member is provided on the same side as the first casing member with a relay module mounting section having a side opening and extending downward. An ECU mounting frame extends from a bottom wall of the second casing member. An ECU is disposed on a second side of a bottom wall of the second casing member and in parallel with the relay module mounting section. A fuse module is attached to the fuse module mounting section to receive fuses. A relay module is attached to the relay module mounting section to receive relays. The fuse module and relay module that generate heat are disposed on a side of the casing in a vertical direction.Type: GrantFiled: January 22, 2008Date of Patent: June 8, 2010Assignee: Sumitomo Wiring Systems, Ltd.Inventor: Katsuya Ito
-
Patent number: 7719117Abstract: A semiconductor device includes a semiconductor substrate, a lower wiring layer formed on the semiconductor substrate, a first interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.Type: GrantFiled: July 26, 2007Date of Patent: May 18, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiro Ishida, Hiroshi Sugiura, Makoto Hasegawa, Katsuya Ito
-
Patent number: 7592892Abstract: A fusible link unit includes a bus bar adapted to be connected to a battery without interposing a fuse between the bus bar and the battery, and a heat resistant insulating sheet which covers at least an upper edge portion of the bus bar. The fusible link unit is adapted to be accommodated inside an in-vehicle electrical connection box.Type: GrantFiled: March 30, 2007Date of Patent: September 22, 2009Assignees: Sumitomo Wiring Systems, Ltd., Pacific Engineering Corp.Inventors: Katsuya Ito, Akira Hirata, Manabu Ohta
-
Patent number: 7572713Abstract: A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the substrate, the trenches having opening widths different from each other. The trench with a smaller opening width is formed so as to have a first depth and the trench with a larger opening width has a bottom including opposite ends each of which has a second depth deeper than the first depth and a central portion shallower than the second depth.Type: GrantFiled: July 27, 2007Date of Patent: August 11, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Katsuya Ito, Hiroaki Tsunoda, Takanori Matsumoto
-
Patent number: 7557422Abstract: A semiconductor device includes a semiconductor substrate including a memory cell region and a peripheral circuit region, a first trench formed in the memory cell region and having a first depth and a first opening width, and a second trench formed in the peripheral circuit region and including a pair of bottom edge portions and a bottom middle portion located between the bottom edge portions. The second trench has a second opening width that is larger than the first opening width. Each bottom edge portion has a second depth that is larger than the first depth. The bottom middle portion has a third depth that is same as the first depth.Type: GrantFiled: July 27, 2007Date of Patent: July 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Katsuya Ito, Hiroaki Tsunoda, Takanori Matsumoto
-
Patent number: 7544065Abstract: An electrical junction box includes a printed board, a broad bus bar for a power source circuit, a plurality of output side connecting terminal members, and a casing for containing the printed board, broad bus bar, and terminal members. A plurality of fuses are mounted on fuse-containing sections in parallel with one another. The broad bus bar for a power source circuit has a vertical portion and a horizontal portion extending from an upper end of the vertical portion to form an inverted L-shaped configuration. The output side connecting terminal members are disposed in a space covered with the broad bus bar. The broad bus bar is provided with a window so that a soldered condition of the output side connecting terminal members can be seen through the window.Type: GrantFiled: January 29, 2008Date of Patent: June 9, 2009Assignee: Sumitomo Wiring Systems, Ltd.Inventor: Katsuya Ito
-
Publication number: 20080284057Abstract: A film roll of a heat-shrinkable polyester film meeting the following requirements: (1) when samples are cut off therefrom at an almost equal interval along the longitudinal direction, and immersed in hot water at 85° C. for 10 seconds, subsequently in water at 25° C. and withdrawn, heat-shrinkage percentages in the maximum shrinkage direction of all the samples are 20% or more; and (2) when raw polymers used for production of the film above comprises of a major constitutional unit and one or more sub constitutional units different therefrom, and the content of the primary sub constitutional unit in each sample is more than 7 mole % in 100% of all constitutional units, and the contents of the primary sub constitutional unit of all the samples fall within a range of ±2 mole % relative to the average.Type: ApplicationFiled: November 1, 2007Publication date: November 20, 2008Inventors: Satoshi Hayakawa, Norimi Tabota, Yoshinori Takegawa, Katsuya Ito, Shigeru Komeda, Katsuhiko Nose
-
Publication number: 20080254654Abstract: An electrical junction box includes a printed board, a broad bus bar for a power source circuit, a plurality of output side connecting terminal members, and a casing for containing the printed board, broad bus bar, and terminal members. A plurality of fuses are mounted on fuse-containing sections in parallel with one another. The broad bus bar for a power source circuit has a vertical portion and a horizontal portion extending from an upper end of the vertical portion to form an inverted L-shaped configuration. The output side connecting terminal members are disposed in a space covered with the broad bus bar. The broad bus bar is provided with a window so that a soldered condition of the output side connecting terminal members can be seen through the window.Type: ApplicationFiled: January 29, 2008Publication date: October 16, 2008Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventor: Katsuya Ito
-
Publication number: 20080247133Abstract: A casing includes a first casing member and a second casing member. The first casing member is provided on a side with a fuse module mounting section having a side opening. The second casing member is provided on the same side as the first casing member with a relay module mounting section having a side opening and extending downward. An ECU mounting frame extends from a bottom wall of the second casing member. An ECU is disposed on a second side of a bottom wall of the second casing member and in parallel with the relay module mounting section. A fuse module is attached to the fuse module mounting section to receive fuses. A relay module is attached to the relay module mounting section to receive relays. The fuse module and relay module that generate heat are disposed on a side of the casing in a vertical direction.Type: ApplicationFiled: January 22, 2008Publication date: October 9, 2008Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventor: Katsuya ITO
-
Patent number: 7399518Abstract: The present invention provides a polyester film superior in heat resistance, chemical resistance, insulation property and thermal dimensional stability, and suitable for application to fields associated with boiling or retort treatment, which require tenacity, pinhole resistance, bending resistance, bag breakage resistance on dropping, impact resistance and the like, fields requiring thermoforming or vacuum forming, and various uses such as packaging bags for water-containing food, pharmaceutical products and the like. [Solving Means] The polyester film characteristically shows an initial elastic modulus in at least one direction of 2.5-10 GPa, an impact strength of 40-10000 J/mm, a thermal shrinkage in at least one direction at 150° C. of ?0.5% to 6%, a haze of 0.001% to 7%, and an absolute value of the difference in the thermal shrinkage between the longitudinal direction and the transverse direction of not more than 1.1%.Type: GrantFiled: August 3, 2004Date of Patent: July 15, 2008Assignee: Toyo Boseki Kabushiki KaishaInventors: Katsuya Ito, Yukinobu Mukoyama
-
Publication number: 20080036089Abstract: A semiconductor device includes a semiconductor substrate, and an interlayer wiring structure further including a lower wiring layer formed on the semiconductor substrate, a first interlayer an interlayer wiring layer including an interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.Type: ApplicationFiled: July 26, 2007Publication date: February 14, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiro ISHIDA, Hiroshi Sugiura, Makoto Hasegawa, Katsuya Ito
-
Publication number: 20070262394Abstract: A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the substrate, the trenches having opening widths different from each other. The trench with a smaller opening width is formed so as to have a first depth and the trench with a larger opening width has a bottom including opposite ends each of which has a second depth deeper than the first depth and a central portion shallower than the second depth.Type: ApplicationFiled: July 27, 2007Publication date: November 15, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuya ITO, Hiroaki Tsunoda, Takanori Matsumoto
-
Publication number: 20070264823Abstract: A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the substrate, the trenches having opening widths different from each other. The trench with a smaller opening width is formed so as to have a first depth and the trench with a larger opening width has a bottom including opposite ends each of which has a second depth deeper than the first depth and a central portion shallower than the second depth.Type: ApplicationFiled: July 27, 2007Publication date: November 15, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuya ITO, Hiroaki Tsunoda, Takanori Matsumoto
-
Publication number: 20070241857Abstract: A fusible link unit includes a bus bar adapted to be connected to a battery without interposing a fuse between the bus bar and the battery, and a heat resistant insulating sheet which covers at least an upper edge portion of the bus bar. The fusible link unit is adapted to be accommodated inside an in-vehicle electrical connection box.Type: ApplicationFiled: March 30, 2007Publication date: October 18, 2007Applicants: SUMITOMO WIRING SYSTEMS, LTD., PACIFIC ENGINEERING CORPORATIONInventors: Katsuya Ito, Akira Hirata, Manabu Ohta
-
Patent number: 7268069Abstract: A method of fabricating a semiconductor device includes forming a lower wiring layer on a semiconductor substrate, forming an interlayer insulating film on the lower wiring layer, layer, forming a plurality of. contact plugs in the interlayer insulating film so that the contact plugs are brought into electrical contact with the lower wiring layer, thereby forming an interlayer wiring layer, forming an upper wiring, layer on the interlayer wiring layer so that the upper wiring layer is brought into electrical contact with the contact plugs, and patterning the upper wiring layer so that the upper wiring layer corresponds to the contact plugs. In the patterning, after the upper wiring layer has been etched, the exposed interlayer insulating film and the exposed contact plugs are etched.Type: GrantFiled: November 16, 2004Date of Patent: September 11, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiro Ishida, Hiroshi Sugiura, Makoto Hasegawa, Katsuya Ito
-
Patent number: D551174Type: GrantFiled: March 21, 2006Date of Patent: September 18, 2007Assignees: Pacific Engineering Corp., Sumitomo Wiring Systems, Ltd.Inventors: Manabu Ohta, Hideki Shibata, Katsuya Ito
-
Patent number: D560172Type: GrantFiled: April 27, 2007Date of Patent: January 22, 2008Assignees: Pacific Engineering Corp., Sumitomo Wiring Systems, Ltd.Inventors: Manabu Ohta, Hideki Shibata, Katsuya Ito