Abstract: A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell; a reference signal generation circuit; a sense amplifier; a first transistor configured to electrically couple the memory cell and a first input terminal of the sense amplifier; a second transistor configured to electrically couple the reference signal generation circuit and a second input terminal of the sense amplifier; a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor; a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; and a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor.

Abstract: According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.

Abstract: According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.

Abstract: A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense amplifier. The memory cell includes a resistance change element. The reference voltage generating circuit generates a reference adjustment voltage. The first transistor provides a reference current in accordance with the reference adjustment voltage. The sense amplifier compares a cell current flowing through the memory cell with the reference current flowing through the first transistor.

Abstract: According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information.

Abstract: According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.

Abstract: Disclosed is an electronic device including a semiconductor memory. The semiconductor memory includes a bit line, a source line, a plurality of resistive memory cells among which a selected resistive memory cell forms a current path between the bit line and the source line, a sense amplifier suitable for sensing data of the bit line in an active operation, a latch suitable for latching data sensed by the sense amplifier in the active operation, a write control unit suitable for comparing data latched in the latch with write data in a write operation, and a write driver suitable for driving the bit line and the source line based on a comparison result of the write control unit and the write data in the write operation.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.

Abstract: According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information.

Abstract: According to one embodiment, a resistance change memory comprises a memory cell array, an error checking and correcting (ECC) circuit and a controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The error checking and correcting (ECC) circuit performs an ECC operation to detect an error in data read from the memory cells and correct the error. The controller performs the ECC operation by the ECC circuit at a predetermined period.

Abstract: According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.

Abstract: The present invention relates to a thermochromic color-memory toner containing: a microcapsule pigment encapsulating a thermochromic color-memory composition; and a binder resin, in which the microcapsule pigment shows a hysteresis characteristic that, in a temperature-rise process, decoloration starts when the temperature reaches t3 and the pigment completely reaches a decolored state in a temperature region of t4 or higher, and in a temperature-drop process, coloration starts when the temperature reaches t2 and the pigment completely reaches a colored state in a temperature region of ti or lower, and ti is in a range of from ?50 to 0° C. and t4 is in a range of from 50 to 150° C.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.

Abstract: The present invention relates to a reversibly thermochromic aqueous ink composition comprising: water; a water-soluble organic solvent; a reversibly thermochromic microcapsule pigment which contains a reversibly thermochromic composition comprising: (A) an electron donating coloring organic compound, (B) an electron accepting compound, and (C) a reaction medium which determines temperature at which color reactions between the components (A) and (B) occur; a comb type polymer dispersant having carboxyl groups on its side chains, an organic nitrogen sulfur compound, and a water-soluble resin, a writing instrument using the ink composition, and a writing instrument set comprising the writing instrument and a frictional body.