Patents by Inventor Katsuyuki Fujita
Katsuyuki Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7794631Abstract: A thermochromic coloring color-memory composition which comprises a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) an ester compound represented by the specific formula as a reaction medium which controls color reactions of the components (A) and (B).Type: GrantFiled: May 14, 2004Date of Patent: September 14, 2010Assignee: The Pilot Ink Co., Ltd.Inventor: Katsuyuki Fujita
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Publication number: 20100177573Abstract: A memory includes a latch circuit latching data from a first and a second bit lines to a first and a second sense nodes; a first data line reading-out the data from the first sense node to an outside; a second data line reading-out the data from the second sense node to the outside; a first write transistor connected between the first bit line and the first or second data line without via the first and second sense node; and a second write transistor connected between the second bit line and the first or second data line without via the first and second sense node, wherein in a write operation, the first write transistor transmits the data from the first or second data line to the first bit line, or the second write transistor transmits the data from the first or second data line to the second bit line.Type: ApplicationFiled: January 8, 2010Publication date: July 15, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fumiyoshi MATSUOKA, Katsuyuki FUJITA, Ryo FUKUDA, Takashi OHSAWA
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Patent number: 7708913Abstract: A thermochromic coloring color-memory composition which comprises a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) an ester compound represented by the specific formula as a reaction medium which controls color reactions of the components (A) and (B).Type: GrantFiled: October 22, 2008Date of Patent: May 4, 2010Assignee: The Pilot Ink Co., Ltd.Inventor: Katsuyuki Fujita
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Publication number: 20100098475Abstract: Provided are a writing instrument produced at a lower cost than conventional thermochromic writing instruments utilizing frictional heat, slim like a pencil and not bulky because it contains an ink directly in a barrel thereof, and excellent in portability; and a set of the writing instruments. The writing instrument 1 is obtained by directly filling a barrel thereof with an ink 2 which becomes colorless or colored, or undergoes a color change by heating and an ink follower 5 following the ink with its consumption; firmly fixing a writing tip portion 3 to the end of the barrel directly or via a relay member; and disposing a friction body 6 having an elasticity at the rear end portion of the barrel. The writing instrument set has a plurality of the writing instruments respectively different from each other in color tone.Type: ApplicationFiled: October 16, 2007Publication date: April 22, 2010Applicant: THE PILOT INK CO., LTDInventors: Katsuyuki Fujita, Youichi Takasu, Kuniyuki Senga
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Patent number: 7675793Abstract: This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells; a sense node pair connected to the bit line pair and transmitting data stored in the memory cells; transfer gates connected between the bit line pair and the sense node pair; latch circuits latching a high-level potential in one sense node of the sense node pair, and latching a first low-level potential in the other sense node of the sense node pair; and a level shifter applying a second low-level potential lower than the first low-level potential to one bit line of the bit line pair according to the electric potentials latched in the sense node pair at the time of writing data or writing back data.Type: GrantFiled: February 19, 2008Date of Patent: March 9, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Katsuyuki Fujita
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Patent number: 7663941Abstract: This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a pair of sense nodes connected to the bit lines, and transmitting the data of the memory cells; transfer gates connected between the bit lines and the sense nodes; a latch circuit latching a first high level potential to one of the pair of sense nodes, and latching a low level potential to the other sense node of the pair of sense nodes; and a level shifter applying a second high level potential higher than the first high level potential to one of the pair of bit lines according to the potentials latched to the pair of sense nodes during a data write operation or a data write-back operation.Type: GrantFiled: February 21, 2008Date of Patent: February 16, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Katsuyuki Fujita
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Publication number: 20090168576Abstract: A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays.Type: ApplicationFiled: December 24, 2008Publication date: July 2, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuyuki FUJITA, Takashi OHSAWA
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Publication number: 20090147226Abstract: An apparatus and a method for exposing a photosensitive material deposited on the inner surface of a tube such as a circular or polygonal tube to light to form a predetermined exposed pattern are provided. The apparatus includes: a guide rod that is inserted into the inner space of an exposure object and emits an exposure light beam toward the inner side of the exposure object; and a stage for changing the relative positions of the exposure object and the guide rod and/or the relative angle between the exposure object and the guide rod. After the irradiation spot of the exposure light beam is brought into focus and/or is adjusted to an exposure starting point, the exposure light beam is projected onto a predetermined position on the exposure object to form a predetermined exposed pattern of a photosensitive material deposited on the inner surface of the exposure object.Type: ApplicationFiled: December 25, 2006Publication date: June 11, 2009Inventors: Toshiyuki Horiuchi, Katsuyuki Fujita, Takashi Yasuda
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Patent number: 7539069Abstract: This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which transmits data with reversed polarities from each other; a first transfer gate provided between the first bit line and the first sense node; a second transfer gate provided between the second bit line and the second sense node; a latch circuit provided between the first and the second sense nodes; a write signal line activated when the data is written or restore to the cell; and a gate circuit connecting the write signal line to the first bit line and the first sense node to the second bit line, or connecting the write signal line to the second bit line and the second sense node to the first bit line, when the data is written or restore.Type: GrantFiled: May 14, 2007Date of Patent: May 26, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Katsuyuki Fujita
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Publication number: 20090097337Abstract: This disclosure concerns a memory including: memory cells having sources, drains, gates and floating bodies; word lines connected to gates of the memory cells and arranged in a first direction; first bit lines and second bit lines connected to sources or drains of the memory cells and arranged alternately in a second direction intersecting with the first direction; and first and second sense amplifiers provided in correspondence with the first and the second bit lines, wherein in a data reading operation, the first sense amplifier activates the first bit lines to sense data via the first bit lines in a state where voltage of the second bit lines is fixed, and after sensing of the data of the first bit line, the second sense amplifier activates the second bit lines to sense data via the second bit lines in a state where voltage of the first bit lines is fixed.Type: ApplicationFiled: October 9, 2008Publication date: April 16, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuyuki FUJITA
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Publication number: 20090050013Abstract: A thermochromic coloring color-memory composition which comprises a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) an ester compound represented by the specific formula as a reaction medium which controls color reactions of the components (A) and (B).Type: ApplicationFiled: October 22, 2008Publication date: February 26, 2009Applicant: THE PILOT INK CO., LTD.Inventor: Katsuyuki Fujita
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Patent number: 7494537Abstract: A thermochromic coloring color-memory composition comprising a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) a compound represented by the specific formula as a reaction medium which controls color reactions of the components (A) and (B).Type: GrantFiled: November 15, 2005Date of Patent: February 24, 2009Assignee: The Pilot Ink Co., Ltd.Inventors: Yoshiaki Ono, Katsuyuki Fujita
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Patent number: 7480198Abstract: This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to gates of the memory cells; bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells; sense nodes connected to the bit lines and transmitting data of the memory cells; transfer gates connected to between the bit lines and the sense nodes; and latch circuits latching data to the sense nodes, wherein in a data read operation, a selection word line is in an inactive state during a latch period which is from immediately before the latch circuits start a data latch operation until when the transfer gate disconnects the bit lines from the sense nodes after the latch operation, the selection word line being one of the word lines and being connected to selection memory cells from which data is to be read to the sense nodes.Type: GrantFiled: March 1, 2007Date of Patent: January 20, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Katsuyuki Fujita
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Publication number: 20080212377Abstract: This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a pair of sense nodes connected to the bit lines, and transmitting the data of the memory cells; transfer gates connected between the bit lines and the sense nodes; a latch circuit latching a first high level potential to one of the pair of sense nodes, and latching a low level potential to the other sense node of the pair of sense nodes; and a level shifter applying a second high level potential higher than the first high level potential to one of the pair of bit lines according to the potentials latched to the pair of sense nodes during a data write operation or a data write-back operation.Type: ApplicationFiled: February 21, 2008Publication date: September 4, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuyuki FUJITA
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Publication number: 20080198673Abstract: This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells; a sense node pair connected to the bit line pair and transmitting data stored in the memory cells; transfer gates connected between the bit line pair and the sense node pair; latch circuits latching a high-level potential in one sense node of the sense node pair, and latching a first low-level potential in the other sense node of the sense node pair; and a level shifter applying a second low-level potential lower than the first low-level potential to one bit line of the bit line pair according to the electric potentials latched in the sense node pair at the time of writing data or writing back data.Type: ApplicationFiled: February 19, 2008Publication date: August 21, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuyuki Fujita
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Publication number: 20080165558Abstract: A semiconductor memory device has memory cells each of which has a MIS type of transistor capable of setting one of two kinds of threshold potentials, reference cells used for determining data stored in the memory cells, which have the same size, shape and electrical properties as those of the memory cells, word lines connected to gates of the memory cells, reference word lines connected to gates of the reference cells, source line contacts connected to sources of the memory cells and the reference cells, and bit line contacts connected to drains of the memory cells and the reference cells, arrangement order of the source line contact, the word line and bit line contact connected to each of the memory cells is equal to arrangement order of the source line contact, the reference word line and the bit line contact connected to the reference cell corresponding to the memory cell.Type: ApplicationFiled: October 16, 2007Publication date: July 10, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuyuki Fujita, Tomoki Higashi
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Publication number: 20080124164Abstract: A friction body that produces frictional heat allowing development, disappearance or change of color of handwriting formed with a writing instrument for producing thermochromic handwriting, with the friction body having a friction coefficient of 0.2 to 1.0 when rubbed against paper surface, and a writing instrument for use in forming thermochromic handwriting which is equipped with the friction body and a writing instrument set including the friction body and a writing instrument for use in forming thermochromic handwriting.Type: ApplicationFiled: November 28, 2007Publication date: May 29, 2008Applicant: THE PILOT INK CO., LTD.Inventors: Yoshihiro ITO, Shouichi OHKAWA, Katsuyuki FUJITA
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Publication number: 20080080234Abstract: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.Type: ApplicationFiled: February 7, 2007Publication date: April 3, 2008Inventors: Yoshihisa Iwata, Katsuyuki Fujita, Yuui Shimizu
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Patent number: 7335624Abstract: A reversible thermochromic display article which comprises a substrate and, formed thereon, a heat coloration image containing a heat coloration type reversible thermochromic composition which is colored by heating and is decolored by cooling and a heat decoloration image containing a heat decoloration type reversible thermochromic composition which is decolored by heating and is colored by cooling, or having a multilayer structure comprising a heat coloration layer containing the heat coloration type reversible thermochromic composition and a heat decoloration layer containing the heat decoloration type reversible thermochromic composition, wherein the heat coloration type reversible thermochromic composition is a microcapsule composition which contains, enclosed therein, (a) an electron-donating chromatic organic compound, (b)? an electron-accepting compound selected from gallic acid esters, and (c) a reaction medium having a melting point lower than 50° C.Type: GrantFiled: January 27, 2005Date of Patent: February 26, 2008Assignee: The Pilot Ink Co., Ltd.Inventors: Kuniyuki Senga, Katsuyuki Fujita, Shigehiro Koide
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Patent number: 7332109Abstract: A thermally color-developing reversibly thermochromic pigment which shows a uniform color density in the coloring temperature range and also shows an optimal ?H value within a range of from 3 to 40° C. Thermally color-developing reversibly thermochromic pigments of a three component system having a ?H value within a range of from 7 to 40° C. in which at least essential three components including (a) an electron-donating chromic organic compound, (b) a specified compound selected from the gallic acid esters and (c) a reaction medium selected from alcohols, esters, ketones and hydrocarbons; which reversibly generates color reactions of both of the compounds within a specified temperature range and has a melting point of less than 50° C., are microencapsulated, and of a four component system having a ?H value within a range of from 3 to 25° C. in which a compound (d) selected from monomer compounds having a melting point of 50° C. or more or polymer compounds having a softening point of 70° C.Type: GrantFiled: December 20, 2002Date of Patent: February 19, 2008Assignee: The Pilot Ink Co., Ltd.Inventors: Kuniyuki Senga, Katsuyuki Fujita, Shigehiro Koide