Patents by Inventor Kazuaki Kurihara

Kazuaki Kurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050142733
    Abstract: A thin film capacitor is provided which includes a single crystal high dielectric constant dielectric layer. The thin film capacitor has a single crystal silicon substrate, a single crystal intermediate layer epitaxially grown on the single crystal silicon substrate, a single crystal lower electrode epitaxially grown on the single crystal intermediate layer, a single crystal high dielectric constant dielectric layer epitaxially grown on the lower electrode layer, an upper electrode layer formed above the single crystal high dielectric constant dielectric layer, and a plurality of conductor terminals connected to the lower electrode layer and upper electrode layer at a plurality of positions.
    Type: Application
    Filed: February 28, 2005
    Publication date: June 30, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kazuaki Kurihara, Takeshi Shioga, John Baniecki
  • Patent number: 6894396
    Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: May 17, 2005
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara, Yasuo Yamagishi
  • Publication number: 20050098816
    Abstract: The capacitor according to the present invention comprises a lower electrode 18 formed on a base substrate 14, a dielectric film 20 formed on the lower electrode 18, and an upper electrode 28 formed on the dielectric film 20 and including a polycrystalline conduction film 22, and a amorphous conduction film 24 formed on the polycrystalline conduction film 22. Because of the amorphous conduction film 24 included in the upper electrode 28, which can shut off hydrogen and water, hydrogen and water can be prohibited from arriving at the dielectric film 20. Accordingly, the dielectric film 20 of an oxide is prevented from being reduced with hydrogen, and the capacitor can have good electric characteristics.
    Type: Application
    Filed: May 21, 2004
    Publication date: May 12, 2005
    Applicant: FUJITSU LIMITED
    Inventors: John Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 6882516
    Abstract: The present invention comprises the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: April 19, 2005
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 6873038
    Abstract: A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: March 29, 2005
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Karasawa, Kazuaki Kurihara
  • Patent number: 6870710
    Abstract: The present invention aims to provide a compact and lightweight piezoelectric actuator, a driving method involving the piezoelectric actuator that can provide a large displacement at a low voltage, and a compact and lightweight information storage device with a high recording density that incorporates such a piezoelectric actuator and has a small moment of inertia of a head when the head is driven. The piezoelectric actuator according to the present invention has four rod-shaped driving sections. Of the four rod-shaped driving sections, a voltage is applied to the two driving sections located along a diagonal line at a time, and the voltage is applied to the two driving sections located along the other diagonal line at a different time from the time for the first two driving sections, whereby two central sections are rotationally driven relative to two end sections.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: March 22, 2005
    Assignee: Fujitsu Limited
    Inventors: Masaharu Hida, Tsuyoshi Mita, Kazuaki Kurihara
  • Publication number: 20050056878
    Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.
    Type: Application
    Filed: October 28, 2004
    Publication date: March 17, 2005
    Inventors: Takeshi Shioga, John Baniecki, Kazuaki Kurihara
  • Publication number: 20050029569
    Abstract: The present invention comprises the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.
    Type: Application
    Filed: September 15, 2004
    Publication date: February 10, 2005
    Applicant: FUJITSU LIMITED
    Inventors: John Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 6853051
    Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: February 8, 2005
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20040253466
    Abstract: By performing epitaxial growth on a semiconductor substrate while keeping conformity, a membrane multi-layer structure showing increased polarization is provided.
    Type: Application
    Filed: April 27, 2004
    Publication date: December 16, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masao Kondo, Kazuaki Kurihara
  • Publication number: 20040239349
    Abstract: A probe card includes probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.
    Type: Application
    Filed: July 18, 2003
    Publication date: December 2, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yasuo Yamagishi, Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20040214400
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Application
    Filed: May 17, 2004
    Publication date: October 28, 2004
    Inventors: Kouichi Muraoka, Kazuaki Kurihara
  • Patent number: 6803617
    Abstract: The capacitor comprises an lower electrode 22, a dielectric film 30 formed on the lower electrode 22, a floating electrode 20 formed on the dielectric film 30, a dielectric film 50 formed on the floating electrode 40 and having a film orientation different from that of the dielectric film 30, and an upper electrode 80 formed on the dielectric film 50, whereby various characteristics depending on film orientations of the dielectric films can be simultaneously improved.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: October 12, 2004
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 6800519
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: October 5, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Muraoka, Kazuaki Kurihara
  • Publication number: 20040184752
    Abstract: A core layer contains photonic crystals formed by ferroelectric members made of a ferroelectric substance and periodically disposed along a one-dimensional direction or two-dimensional directions. Electrodes apply an electric field to the core layer. An optical function device is provided which can be made compact and can set a wavelength at high speed.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 23, 2004
    Applicants: FUJITSU LIMITED, JAPAN AS REPRESENTED BY THE PRESIDENT OF THE UNIVERSITY OF TOKYO
    Inventors: Tsuyoshi Aoki, Kazuaki Kurihara, Makoto Kuwabara
  • Publication number: 20040178436
    Abstract: An integrated thin film capacitive element comprising a dielectric material of the specified composition that exhibits increased voltage tunability of capacitance and capacitance density and a production process thereof are disclosed. The integrated thin film capacitive element comprises a capacitor structure constituted from a lower electrode, a dielectric layer comprised of the high dielectric constant material represented by the formula: (Ba(1-y)(1-x)Sr(1-y)xYy)Ti1+zO3+&dgr; with the range 0<x<1, 0.007<y<0.02, −1<&dgr;<0.5, and (Ba(1-y)(1-x)+Sr(1-y)x)/Ti1+z<1, and an upper electrode. An electronic device comprising the capacitive element of the present invention is also disclosed.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 16, 2004
    Applicant: FUJITSU LIMITED
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 6781290
    Abstract: A piezoelectric actuator includes a single-crystal piezoelectric thin film having a crystal orientation aligned with the crystal orientation of a single-crystal Si substrate, and first and second electrode films formed on first and second sides of the single-crystal piezoelectric thin film, respectively.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Motoyuki Nishizawa, Masaki Kurasawa, Keishiro Okamoto
  • Patent number: 6769177
    Abstract: A method of producing an ink-jet recording head using ion milling is provided. The method includes the steps of forming a piezoelectric layer subsequent to an electrode layer on a substrate by using a thin-film deposition technology, forming an energy-generating element for generating energy for ink ejection by etching the electrode layer and the piezoelectric layer simultaneously by ion milling, and removing a fence formed by deposits of mixed fine powders including those etched off the electrode layer and the piezoelectric layer.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: August 3, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Shuji Koike, Yoshiaki Sakamoto, Tomohisa Shingai, Seigen Otani, Toshihiko Osada, Kazuaki Kurihara
  • Publication number: 20040140535
    Abstract: The present invention provides a semiconductor device comprising a single-crystal silicon substrate; and a single-crystal oxide thin film having a perovskite structure formed through epitaxial growth on the single-crystal silicon. substrate. The single-crystal oxide thin film is directly in contact with a surface of the single-crystal silicon substrate, and contains a bivalent metal that is reactive to silicon.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 22, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masao Kondo, Kazuaki Kurihara, Kenji Maruyama, Hideki Yamawaki
  • Publication number: 20040130849
    Abstract: In one aspect of the invention, in a thin layer capacitor element comprising a capacitor having a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.
    Type: Application
    Filed: November 13, 2003
    Publication date: July 8, 2004
    Inventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Mamoru Kurashina