Patents by Inventor Kazuaki Kurihara

Kazuaki Kurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7937830
    Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: May 10, 2011
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
  • Patent number: 7940516
    Abstract: A capacitor including a substrate; a conductive layer provided on the substrate and containing conductive particles; a valve metal sheet having a dielectric part formed throughout an entire surface of the conductive layer; a protection layer covering the valve metal sheet; a first electrode terminal electrically connected to the conductive layer and partially exposed from an external surface of the protection layer; and a second electrode terminal electrically connected to a surface of the valve metal sheet which is opposite to a surface of the valve metal sheet on which the dielectric part is provided, and the second electrode terminal partially exposed from the external surface of the protection layer; wherein the dielectric part is made of an oxide of a metallic material of the valve metal sheet, the dielectric part is formed with a corrugated surface on the conductive layer, and the conductive particles of the conductive layer are in contact with the corrugated surface of the dielectric part.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 10, 2011
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 7935996
    Abstract: In a BST thin film being a capacitor film in a capacitor element, the capacitor film is formed such that two kinds of chemical states of Sr(I) and Sr(II) exist at a portion of which depth is up to 2.5 nm from a surface thereof (surface layer portion of which thickness is 2.5 nm), an average concentration of Sr(I) is set as AC(I), an average concentration of Sr(II) is set as AC(II), and when “R=AC(II)/AC(I)”, a value of “R” is adjusted to be “0” (zero)<R?0.3, more preferably, “0” (zero)<R?0.1.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: May 3, 2011
    Assignee: Fujitsu Limited
    Inventors: John D. Baniecki, Kazuaki Kurihara, Masatoshi Ishii
  • Patent number: 7927998
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
  • Publication number: 20110073993
    Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.
    Type: Application
    Filed: December 7, 2010
    Publication date: March 31, 2011
    Applicant: FUJITSU LIMITED
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20110056068
    Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 10, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Patent number: 7867869
    Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: January 11, 2011
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 7863524
    Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: January 4, 2011
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Patent number: 7858959
    Abstract: A laminated film structure, method of manufacturing, and a preferable electronic element using the structure. The effective polarization into the electric field can be realized in the direction of crystal axis by enhancing the crystal property and alignment property of the ferroelectric substance film formed through epitaxial growth with reference to the plane alignment of semiconductor substrate. After the yttrium stabilized zirconium film and a film of the rock salt structure are sequentially formed with epitaxial growth on a semiconductor substrate, the ferroelectric substance film of simple Perovskite structure is also formed with epitaxial growth. The ferroelectric substance film can improve the crystal property and alignment property thereof by rotating the plane for 45 degrees within the plane for the crystal axis of the yttrium stabilized zirconium.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: December 28, 2010
    Assignee: Fujitsu Limited
    Inventors: Masao Kondo, Kazuaki Kurihara
  • Publication number: 20100321911
    Abstract: A capacitor including a substrate; a conductive layer provided on the substrate and containing conductive particles; a valve metal sheet having a dielectric part formed throughout an entire surface of the conductive layer; a protection layer covering the valve metal sheet; a first electrode terminal electrically connected to the conductive layer and partially exposed from an external surface of the protection layer; and a second electrode terminal electrically connected to a surface of the valve metal sheet which is opposite to a surface of the valve metal sheet on which the dielectric part is provided, and the second electrode terminal partially exposed from the external surface of the protection layer; wherein the dielectric part is made of an oxide of a metallic material of the valve metal sheet, the dielectric part is formed with a corrugated surface on the conductive layer, and the conductive particles of the conductive layer are in contact with the corrugated surface of the dielectric part.
    Type: Application
    Filed: August 4, 2010
    Publication date: December 23, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi SHIOGA, Kazuaki KURIHARA
  • Patent number: 7846852
    Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: December 7, 2010
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Masataka Mizukoshi, Kazuaki Kurihara
  • Patent number: 7832069
    Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed on a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: November 16, 2010
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20100264951
    Abstract: Recesses are formed on one surface of a substrate. A conductive film covers an inner surface of each of the recesses. This conductive film contacts a bump of a semiconductor device to be inspected and is electrically connected to the bump. It is therefore possible to prevent damages of the bump to be caused by contact of a probe pin.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 21, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20100233796
    Abstract: A fuel cell system includes a fuel cell configured to generate electric power with a fuel gas and an oxygen gas fed to the fuel cell and to discharge exhaust gas including CO2 as a result of generating the electric power; a CO extraction part configured to reduce the CO2 in the exhaust gas fed to the CO extraction part to CO, the CO extraction part including a processing container fed with the exhaust gas and a CO2 adsorbing member provided in the processing container and formed of an oxide having an oxygen deficiency; and a CO recycling part configured to feed the extracted CO to the fuel cell as part of the fuel gas.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 16, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Kazuaki KURIHARA, John David Baniecki, Masatoshi Ishii
  • Publication number: 20100233359
    Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).
    Type: Application
    Filed: May 19, 2010
    Publication date: September 16, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi SHIOGA, Masataka MIZUKOSHI, Kazuaki KURIHARA
  • Patent number: 7795739
    Abstract: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: September 14, 2010
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Takeshi Shioga, John D. Baniecki
  • Patent number: 7793396
    Abstract: A manufacturing method includes forming a dielectric part by oxidizing an entire first surface of a valve metal sheet; forming a through hole in the valve metal sheet in which the dielectric part is formed; applying an adhesive conductive material to a surface of a substrate; attaching the valve metal sheet in which the through hole is formed, to the substrate so that the first surface contacts the conductive material on the substrate surface; forming a conductive layer by curing the conductive material; forming a protection layer which covers a second surface of the valve metal sheet which is opposite to the first surface of the valve metal sheet; forming openings in the protection layer, so that the conductive layer in the through hole and the second surface of the valve metal sheet are partially exposed from the openings; and filling up the openings in the protection layer with another conductive material to form electrode terminals.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: September 14, 2010
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 7778009
    Abstract: A thin-film capacitor element having two conductive films and a dielectric film sandwiched therebetween is provided above a substrate. An inorganic protective film covering the thin-film capacitor element and having a second opening exposing at least a part of the conductive films is provided. An organic protective film covering the thin-film capacitor element from above the inorganic protective film and having a first opening therein, which is larger than the second opening and exposes the second opening, is provided. Besides, a bump connected with the conductive films via the first opening and the second opening is provided.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: August 17, 2010
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Masatoshi Ishii, Kazuaki Kurihara, Teru Nakanishi, Masataka Mizukoshi
  • Patent number: 7745924
    Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: June 29, 2010
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Masataka Mizukoshi, Kazuaki Kurihara
  • Patent number: 7737511
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushikik Kaisha Toshiba
    Inventors: Kouichi Muraoka, Kazuaki Kurihara