Patents by Inventor Kazufumi Watanabe

Kazufumi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8743252
    Abstract: A solid-state imaging device according to an embodiment of the present invention includes plural pixels, in which each pixel includes: a transfer transistor that transfers electric charge from a photoelectric conversion section to a floating diffusion section; a reset transistor that resets the floating diffusion section; a amplifying transistor that outputs a signal based on the electric charge held by the floating diffusion section; a selection transistor that is provided at the output side of the amplifying transistor and selects a pixel; and a charge storage capacitor that is provided between the amplifying transistor and the selection transistor and stores the quantity of electric charge on the basis the quantity of the electric charge held by the floating diffusion section through the charge-discharge behavior of electric charge through a current source.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventor: Kazufumi Watanabe
  • Patent number: 8704324
    Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 22, 2014
    Assignee: Sony Corporation
    Inventors: Susumu Hiyama, Kazufumi Watanabe
  • Patent number: 8660151
    Abstract: An encoding apparatus 2 includes: an encoding unit 21 that encodes and multiplexes a video signal V2, an audio signal A2 and a data signal D2 to be given to the encoding apparatus 2; a timer 22 that outputs time information T2; a timer adjusting unit 23 that adjusts the timer 22 so that the time information T2 and time information T1 within a multiplexed stream S1 outputted from an encoding apparatus 1 are synchronized with each other; and a multiplexing unit 24 that multiplexes the multiplexed stream S1, an encoded stream S21 outputted from the encoding unit 21 and the time information T2, and outputs the resultant multiplexed stream and information as output of the encoding apparatus 2. Third and subsequent encoding apparatus are configured to have the same configuration as that of the encoding apparatus 2.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: February 25, 2014
    Assignee: NTT Electronics Corporation
    Inventors: Hidetoshi Suzuki, Kazufumi Watanabe, Eiko Sone, Masayoshi Kubozono, Masashi Takada
  • Publication number: 20140012853
    Abstract: A search server includes an extracting unit that extracts a search target matching a search condition based on profile data, and a transmitting unit that transmits the search target to a user terminal. The search condition includes a first frequency of appearance for each of one or more specified topics specified by a user in a first specified period and a second frequency of appearance for each of the specified topics in a second specified period being later than the first specified period. The extracting unit extracts the search target where the frequency of appearance for each of the specified topics in a first search target period and a second search target period being later than the first search target period are identical or similar to the first frequency of appearance and the second frequency of appearance, respectively.
    Type: Application
    Filed: February 24, 2012
    Publication date: January 9, 2014
    Applicant: RAKUTEN, INC.
    Inventors: Kazufumi Watanabe, Makoto Okabe, Rikio Onai, Masahiro Sanjo, Hiromi Hirano
  • Publication number: 20130280848
    Abstract: A solid-state imaging device including a substrate; a wiring layer formed on a front side of the substrate in which pixels are formed; a surface electrode pad section formed in the wiring layer; a light-shielding film formed on a rear side of the substrate; a pad section base layer formed in the same layer as the light-shielding film; an on-chip lens layer formed over the light-shielding film and the pad section base layer in a side opposite from the substrate side; a back electrode pad section formed above the on-chip lens layer; a through-hole formed to penetrate the on-chip lens layer, the pad section base layer, and the substrate so as to expose the surface electrode pad section; and a through-electrode layer which is formed in the through-hole and connects the surface electrode pad section and the back electrode pad section.
    Type: Application
    Filed: June 18, 2013
    Publication date: October 24, 2013
    Inventor: Kazufumi Watanabe
  • Patent number: 8564701
    Abstract: A solid-state imaging device includes a pixel including a buried photodiode formed inside a substrate, a buried floating diffusion formed at a depth equal to that of the buried photodiode in the substrate so as to face a bottom of a trench portion formed in the substrate, and a buried gate electrode formed at the bottom of the trench portion in order to transfer a signal charge from the buried photodiode to the buried floating diffusion.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: October 22, 2013
    Assignee: Sony Corporation
    Inventors: Taiichiro Watanabe, Kazufumi Watanabe
  • Publication number: 20130234276
    Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 12, 2013
    Applicant: Sony Corporation
    Inventors: Susumu Hiyama, Kazufumi Watanabe
  • Patent number: 8492864
    Abstract: A solid-state imaging device includes: a substrate; a wiring layer formed on a front side of the substrate in which pixels are formed; a surface electrode pad section formed in the wiring layer; a light-shielding film formed on a rear side of the substrate; a pad section base layer formed in the same layer as the light-shielding film; an on-chip lens layer formed over the light-shielding film and the pad section base layer in a side opposite from the substrate side; a back electrode pad section formed above the on-chip lens layer; a through-hole formed to penetrate the on-chip lens layer, the pad section base layer, and the substrate so as to expose the surface electrode pad section; and a through-electrode layer which is formed in the through-hole and connects the surface electrode pad section and the back electrode pad section.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: July 23, 2013
    Assignee: Sony Corporation
    Inventor: Kazufumi Watanabe
  • Patent number: 8445985
    Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 21, 2013
    Assignee: Sony Corporation
    Inventors: Susumu Hiyama, Kazufumi Watanabe
  • Publication number: 20130100811
    Abstract: An output rate controller has a TS packet buffer, a maximum value increase detector, a minimum value decrease detector and an output controller. The TS packet buffer accumulates input packets. The maximum value increase detector detects an increasing trend of the maximum number of packets being accumulated in the TS packet buffer within a fixed time period. The minimum value decrease detector detects a decreasing trend of the minimum number of packets being accumulated in the TS packet buffer within a fixed time period. The output controller sets a higher output rate of packets being accumulated in the TS packet buffer if an increasing trend has been detected by the maximum value increase detector, and sets a lower output rate of packets being accumulated in the TS packet buffer if a decreasing trend has been detected by the minimum value decrease detector.
    Type: Application
    Filed: May 30, 2011
    Publication date: April 25, 2013
    Applicant: NTT Electronics Corporation
    Inventors: Kazufumi Watanabe, Toshihisa Yajima
  • Patent number: 8314376
    Abstract: A solid-state imaging device having unit pixels arranged therein is provided, each unit pixel including: a transfer transistor configured to transfer a charge from a photoelectric conversion part to a floating diffusion part; a first reset transistor configured to reset the floating diffusion part; a charge storage capacitor; a charging transistor configured to charge the charge storage capacitor by a current corresponding to a charge in the floating diffusion part; a second reset transistor configured to reset the charge storage capacitor; an amplifying transistor configured to output an electric signal corresponding to a charge in the charge storage capacitor; and a selection transistor configured to selectively cause the amplifying transistor to be in an operation state.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: November 20, 2012
    Assignee: Sony Corporation
    Inventor: Kazufumi Watanabe
  • Patent number: 8272879
    Abstract: The present invention provides a planar connector having excellent performances including flatness, warp-deformation resistance, and heat resistance, being capable of responding to shape changes in recent planar connectors. Specifically, the planar connector is composed of a composite resin composition comprises (A) a liquid crystalline polymer containing 55% by mole or less of p-hydroxy benzoic acid residue and having a melting point of 330° C. or higher, (B) a plate-like inorganic filler, and (C) a fibrous filler having a weight average fiber length within a range of 250 to 600 ?m, the amount of (B) component being 25 to 35% by weight to the total composition, the amount of (C) component being 10 to 25% by weight to the total composition, the sum in total of (B) component and (C) component being 40 to 50% by weight to the total composition, wherein the connector has a lattice structure inside an outer frame, and has an opening inside the lattice area, and wherein the pitch interval of the lattice area is 1.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: September 25, 2012
    Assignee: Polyplastics Co., Ltd.
    Inventors: Hiroki Fukatsu, Raita Nishikawa, Hirokazu Ohshiba, Seiji Kayukawa, Kazufumi Watanabe
  • Publication number: 20120207182
    Abstract: An encoding apparatus 2 includes: an encoding unit 21 that encodes and multiplexes a video signal V2, an audio signal A2 and a data signal D2 to be given to the encoding apparatus 2; a timer 22 that outputs time information T2; a timer adjusting unit 23 that adjusts the timer 22 so that the time information T2 and time information T1 within a multiplexed stream S1 outputted from an encoding apparatus 1 are synchronized with each other; and a multiplexing unit 24 that multiplexes the multiplexed stream S1, an encoded stream S21 outputted from the encoding unit 21 and the time information T2, and outputs the resultant multiplexed stream and information as output of the encoding apparatus 2. Third and subsequent encoding apparatus are configured to have the same configuration as that of the encoding apparatus 2.
    Type: Application
    Filed: September 22, 2010
    Publication date: August 16, 2012
    Applicant: NTT Electronics Corporation
    Inventors: Hidetoshi Suzuki, Kazufumi Watanabe, Eiko Sone, Masayoshi Kubozono, Masashi Takada
  • Publication number: 20120086094
    Abstract: A solid-state imaging device includes: a substrate; a wiring layer formed on a front side of the substrate in which pixels are formed; a surface electrode pad section formed in the wiring layer; a light-shielding film formed on a rear side of the substrate; a pad section base layer formed in the same layer as the light-shielding film; an on-chip lens layer formed over the light-shielding film and the pad section base layer in a side opposite from the substrate side; a back electrode pad section formed above the on-chip lens layer; a through-hole formed to penetrate the on-chip lens layer, the pad section base layer, and the substrate so as to expose the surface electrode pad section; and a through-electrode layer which is formed in the through-hole and connects the surface electrode pad section and the back electrode pad section.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 12, 2012
    Applicant: SONY CORPORATION
    Inventor: Kazufumi Watanabe
  • Patent number: 8123978
    Abstract: The present invention provides a liquid crystalline polyester resin composition which imparts a good mold-releasability during molding and further is improved in heat resistance. Specifically, with 100 parts by weight of a liquid crystalline polyester resin is added 0.001 to 1 part by weight of a fatty acid ester which is a tetraester of pentaerythritol and a C10 to C32 higher fatty acid and has an acid value ranging from 0.01 to 0.5 and a hydroxyl value ranging from 0.01 to 5.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: February 28, 2012
    Assignee: Polyplastics Co., Ltd.
    Inventors: Kazufumi Watanabe, Hirokazu Ohshiba, Raita Nishikawa, Kenichi Yasusaka
  • Publication number: 20110241148
    Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.
    Type: Application
    Filed: March 24, 2011
    Publication date: October 6, 2011
    Applicant: SONY CORPORATION
    Inventors: Susumu Hiyama, Kazufumi Watanabe
  • Publication number: 20110086968
    Abstract: The present invention provides a planar connector having excellent performances including flatness, warp-deformation resistance, and heat resistance, being capable of responding to shape changes in recent planar connectors. Specifically, the planar connector is composed of a composite resin composition comprises (A) a liquid crystalline polymer containing 55% by mole or less of p-hydroxy benzoic acid residue and having a melting point of 330° C. or higher, (B) a plate-like inorganic filler, and (C) a fibrous filler having a weight average fiber length within a range of 250 to 600 ?m, the amount of (B) component being 25 to 35% by weight to the total composition, the amount of (C) component being 10 to 25% by weight to the total composition, the sum in total of (B) component and (C) component being 40 to 50% by weight to the total composition, wherein the connector has a lattice structure inside an outer frame, and has an opening inside the lattice area, and wherein the pitch interval of the lattice area is 1.
    Type: Application
    Filed: May 19, 2009
    Publication date: April 14, 2011
    Inventors: Hiroki Fukatsu, Raita Nishikawa, Hirokazu Ohshiba, Seiji Kayukawa, Kazufumi Watanabe
  • Patent number: 7897083
    Abstract: The object is to provide a method for manufacturing liquid crystalline resin composition having a hollow filler and a fibrous filler using a common melting-kneading extruder to maintain well-balanced relation between the residual percentages of hollow filler and the fiber length, which balance could not be attained in the prior art. A liquid crystalline resin composition having 5 to 30% by weight of hollow filler and 5 to 30% by weight of fibrous filler is manufactured using a melting-kneading extruder provided with a screw. (1) The liquid crystalline resin is fed from a main feed port located at upstream side in the extruding direction, while a hollow filler and a fibrous filler are fed from a side feed port located at downstream side in the extruding direction.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: March 1, 2011
    Assignee: Polyplastics Co., Ltd.
    Inventors: Hiroki Fukatsu, Masayuki Sakai, Kazufumi Watanabe
  • Publication number: 20110019063
    Abstract: A solid-state imaging device includes a pixel including a buried photodiode formed inside a substrate, a buried floating diffusion formed at a depth equal to that of the buried photodiode in the substrate so as to face a bottom of a trench portion formed in the substrate, and a buried gate electrode formed at the bottom of the trench portion in order to transfer a signal charge from the buried photodiode to the buried floating diffusion.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 27, 2011
    Applicant: SONY CORPORATION
    Inventors: Taiichiro Watanabe, Kazufumi Watanabe
  • Patent number: 7863713
    Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: January 4, 2011
    Assignees: Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Kazufumi Watanabe