Patents by Inventor Kazuhide Tomiyasu
Kazuhide Tomiyasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170160403Abstract: An aim of the present invention is to provide a technology to inhibit degradation phenomena of TFTs in an imaging panel having such TFTs in each pixel. The imaging panel captures scintillation light, which are X-rays that have passed through a specimen and been converted by a scintillator. The imaging panel includes a plurality of gate lines and a plurality of data lines. The imaging panel includes a conversion element that converts scintillation light to electric charge, a thin film transistor connected to the gate line, data line, and conversion element, and a metal wiring line connecting to the conversion element and supplying a bias voltage to the conversion element. The metal wiring line is positioned approximately parallel to the data line so as to overlap the top of the thin film transistor.Type: ApplicationFiled: June 25, 2015Publication date: June 8, 2017Applicant: Sharp Kabushiki KaishaInventors: Kazuhide TOMIYASU, Shigeyasu MORI
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Publication number: 20170154916Abstract: An aim of the present invention is to make it possible to achieve stable operation of thin film transistors in an imaging panel of an X-ray imaging system that uses an indirect conversion scheme. An imaging panel includes a substrate, thin film transistor, photoelectric conversion element, and bias wiring line. The thin film transistor is formed on the substrate. The photoelectric conversion element is connected to the thin film transistor and irradiated by scintillation light. The bias wiring line is connected to the photoelectric conversion element and applies a reverse bias voltage to the photoelectric conversion element. The thin film transistor includes a semiconductor active layer and a gate electrode. The gate electrode is formed between the substrate and semiconductor active layer. The bias wiring line includes a portion that overlaps the gate electrode and semiconductor active layer as seen from the radiation direction of the scintillation light.Type: ApplicationFiled: June 25, 2015Publication date: June 1, 2017Applicant: Sharp Kabushiki KaishaInventors: Shigeyasu MORI, Kazuhide TOMIYASU
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Publication number: 20170154914Abstract: An aim of the present invention is to provide a technology that increases the aperture ratio of an imaging panel. The imaging panel captures scintillation light, which are X-rays that have passed through a specimen and been converted by a scintillator. The imaging panel includes a plurality of gate lines and a plurality of data lines. The imaging panel includes, in each of the pixels, a conversion element that converts scintillation light to electric charge, a thin film transistor connected to the gate line, data line, and conversion element, and a metal wiring line connecting to the conversion element and supplying a bias voltage to the conversion element. The metal wiring line is positioned generally parallel to the data line and is closer to the data line that connects to the thin film transistor than approximately the center in the extension direction of the gate line of the conversion element.Type: ApplicationFiled: June 25, 2015Publication date: June 1, 2017Applicant: Sharp Kabushiki KaishaInventors: Kazuhide TOMIYASU, Shigeyasu MORI
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Publication number: 20170154915Abstract: The present invention aims at inhibiting the occurrence of thinning or disconnecting of the bias wiring line in an imaging panel and X-ray imaging device, thereby inhibiting signal delays, signal transmission defects, and the like. A second contact hole electrically connecting an electrode of a photodiode to a bias wiring line penetrates a second interlayer insulating film and photosensitive resin layer. In the second contact hole, an area of a region where the photosensitive resin layer opens is smaller than an area of a region where the second interlayer insulating film opens.Type: ApplicationFiled: June 22, 2015Publication date: June 1, 2017Applicant: Sharp Kabushiki KaishaInventors: Kazuhide TOMIYASU, Shigeyasu MORI
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Publication number: 20170148843Abstract: An aim of the present invention is to improve the conversion efficiency of scintillation light into electric charge by a photoelectric conversion element in an imaging panel of an X-ray imaging system using an indirection conversion scheme. An imaging panel generates images based on scintillation light acquired from X-rays that have passed through a specimen. The imaging panel includes a substrate, thin film transistor, photoelectric conversion element, and reflective layer. The thin film transistor is formed on the substrate. The photoelectric conversion element is connected to the thin film transistor and converts incident scintillation light into electric charge. The entirety of a region of a light-receiving surface of the photoelectric conversion element where the scintillation light is incident overlaps the reflective layer as seen from the incident direction of the scintillation light. The reflective layer may be the drain electrode.Type: ApplicationFiled: June 25, 2015Publication date: May 25, 2017Applicant: Sharp Kabushiki KaishaInventors: Shigeyasu MORI, Kazuhide TOMIYASU
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Publication number: 20170139056Abstract: A second insulating film is disposed so as to cover a conversion element that includes a first insulating film, photodiode, and electrode. The second insulating film is made of a SiNxOy material, where x is greater than 0 and y is greater than or equal to 0. This makes it possible to provide a TFT and photodiode with excellent anti-moisture characteristics.Type: ApplicationFiled: June 22, 2015Publication date: May 18, 2017Applicant: Sharp Kabushiki KaishaInventors: Kazuhide TOMIYASU, Shigeyasu MORI
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Publication number: 20170139057Abstract: An X-ray image pickup system (10) includes an X-ray source (16), an image pickup panel (12), a scintillator (13), and an X-ray control unit (14E). The image pickup panel includes a photoelectric conversion element (26), a capacitor (50), a thin film transistor (24), and TFT control units (14A, 14B, 14F). To the photoelectric conversion element (26), scintillation light is projected. The capacitor (50) is connected to the photoelectric conversion element (26), and accumulates charges. The thin film transistor (24) is connected to the capacitor (50). The TFT control units (14A, 14B, 14F) control an operation of the thin film transistor (24). The thin film transistor (24) includes a semiconductor active layer (32) made of an oxide semiconductor. The X-ray control unit (14E) intermittently projects X-ray to the X-ray source (16). The TFT control units (14A, 14B, 14F) cause the thin film transistor (24) to operate when the X-ray is not projected, so as to read out the charges accumulated in the capacitor (50).Type: ApplicationFiled: June 25, 2015Publication date: May 18, 2017Inventors: Shigeyasu MORI, Kazuhide TOMIYASU
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Publication number: 20170131413Abstract: Provided is a technique that reduces patterning defects of data lines in an imaging panel and drain electrodes in thin film transistors without lowering the aperture ratio of the imaging panel. The imaging panel captures scintillation light, which are X-rays that have passed through a specimen and been converted by a scintillator. The imaging panel includes a plurality of gate lines 11 and a plurality of data lines 12. The imaging panel includes, in each of the pixels 13, a conversion element 15 that converts scintillation light to electric charge, and a thin film transistor 14 connected to the gate line 11, data line 12, and conversion element 15. A drain electrode 144 of the thin film transistor 14 is formed such that edges 144E1 and 144E2 of the drain electrode 144 near the data line 12 are more inside the pixel 13 than edges 15E1 and 15E2 of the conversion element 15 near the data line 12.Type: ApplicationFiled: June 25, 2015Publication date: May 11, 2017Applicant: Sharp Kabushiki KaishaInventors: Kazuhide TOMIYASU, Shigeyasu MORI
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Publication number: 20170092673Abstract: A light detection device includes: a TFT having a semiconductor layer supported on a substrate, a source electrode, a drain electrode, and a gate electrode; a photodiode having a bottom electrode electrically connected to the drain electrode, a semiconductor laminate structure, and a top electrode; and an electrode made of the same conductive film as the bottom electrode and arranged on the semiconductor layer with an insulating layer interposed therebetween.Type: ApplicationFiled: March 19, 2015Publication date: March 30, 2017Applicant: Sharp Kabushiki KaishaInventors: Tadayoshi MIYAMOTO, Kazuhide TOMIYASU, Atsushi TOMYO, Kazuatsu ITO, Shigeyasu MORI
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Patent number: 9508544Abstract: This semiconductor device (100) includes a substrate (10) and a TFT which is provided on the substrate. The TFT includes a gate electrode (12), an oxide semiconductor layer (14) which faces the gate electrode, source and drain electrodes (16, 18) which are connected to the oxide semiconductor layer, and an insulating layer (22) which contacts at least partially with the source and drain electrodes. The insulating layer (22) includes a lower region (22b) which contacts at least partially with the source and drain electrodes and an upper region (22a) which is located over the lower region. The lower region (22b) has a higher hydrogen content than the upper region (22a).Type: GrantFiled: November 9, 2015Date of Patent: November 29, 2016Assignee: Sharp Kabushiki KaishaInventor: Kazuhide Tomiyasu
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Publication number: 20160327825Abstract: According to an embodiment of the present invention, an active matrix substrate manufacturing method includes: a step (a) of forming a thin film transistor on a substrate; a step (b) of forming an interlayer insulating layer covering the thin film transistor; a step (c) of forming a first electrode after the step (b); a step (d) of forming, after the step (c), a photospacer by applying a photosensitive resin material to the substrate and patterning the photosensitive resin material; and a step (e) of performing, after the step (d), plasma processing using a gas that contains a fluorine-based gas but does not contain oxygen gas.Type: ApplicationFiled: August 28, 2014Publication date: November 10, 2016Applicant: Sharp Kabushiki KaishaInventor: Kazuhide TOMIYASU
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Publication number: 20160233309Abstract: This semiconductor device includes a substrate and a thin film transistor supported on the substrate. The thin film transistor includes a gate electrode, a semiconductor layer, a gate-insulating layer provided between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode respectively making contact with the semiconductor layer. The source electrode and the drain electrode respectively include a main layer containing aluminum or copper, a lower layer having a first layer containing refractory metal and positioned at a substrate side of the main layer, and an upper layer having a second layer containing refractory metal. The upper layer is provided so as to cover an upper surface of the main layer and at least the section of the side face of the main layer that overlaps the semiconductor layer.Type: ApplicationFiled: August 12, 2014Publication date: August 11, 2016Applicant: Sharp Kabushiki KaishaInventors: Tadayoshi MIYAMOTO, Kazuhide TOMIYASU
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Publication number: 20160064217Abstract: This semiconductor device (100) includes a substrate (10) and a TFT which is provided on the substrate. The TFT includes a gate electrode (12), an oxide semiconductor layer (14) which faces the gate electrode, source and drain electrodes (16, 18) which are connected to the oxide semiconductor layer, and an insulating layer (22) which contacts at least partially with the source and drain electrodes. The insulating layer (22) includes a lower region (22b) which contacts at least partially with the source and drain electrodes and an upper region (22a) which is located over the lower region. The lower region (22b) has a higher hydrogen content than the upper region (22a).Type: ApplicationFiled: November 9, 2015Publication date: March 3, 2016Inventor: Kazuhide TOMIYASU
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Publication number: 20150171220Abstract: This semiconductor device (100) includes a substrate (10) and a TFT which is provided on the substrate. The TFT includes a gate electrode (12), an oxide semiconductor layer (14) which faces the gate electrode, source and drain electrodes (16, 18) which are connected to the oxide semiconductor layer, and an insulating layer (22) which contacts at least partially with the source and drain electrodes. The insulating layer (22) includes a lower region (22b) which contacts at least partially with the source and drain electrodes and an upper region (22a) which is located over the lower region. The lower region (22b) has a higher hydrogen content than the upper region (22a).Type: ApplicationFiled: April 26, 2013Publication date: June 18, 2015Inventor: Kazuhide Tomiyasu
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Patent number: 8580623Abstract: A TFT (20) includes a semiconductor layer (12s1) of an oxide semiconductor, a source electrode (13sd) and a drain electrode (13dd) provided on the semiconductor layer (12s1) and separated from each other, a gate insulating film (15) covering a portion of the semiconductor layer between the source electrode (13sd) and the drain electrode (13dd), a gate electrode (18gd) provided over the semiconductor layer (12s1) with the gate insulating film (15) being interposed between the gate electrode (18gd) and the semiconductor layer (12s1). The source electrode (13sd) is integrally formed with the source line (13s1). The gate electrode (18gd) is integrally formed with the gate line (18g1). The semiconductor layer (12s1) extends below the source line (13s1). The entireties of the source line (13s1), the source electrode (13sd), and the drain electrode (13dd) are provided on the semiconductor layer (12s1).Type: GrantFiled: November 10, 2011Date of Patent: November 12, 2013Assignee: Sharp Kabushiki KaishaInventors: Kazuhide Tomiyasu, Tomohiro Kimura
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Publication number: 20130234137Abstract: A TFT (20) includes a semiconductor layer (12s1) of an oxide semiconductor, a source electrode (13sd) and a drain electrode (13dd) provided on the semiconductor layer (12s1) and separated from each other, a gate insulating film (15) covering a portion of the semiconductor layer between the source electrode (13sd) and the drain electrode (13dd), a gate electrode (18gd) provided over the semiconductor layer (12s1) with the gate insulating film (15) being interposed between the gate electrode (18gd) and the semiconductor layer (12s1). The source electrode (13sd) is integrally formed with the source line (13s1). The gate electrode (18gd) is integrally formed with the gate line (18g1). The semiconductor layer (12s1) extends below the source line (13s1). The entireties of the source line (13s1), the source electrode (13sd), and the drain electrode (13dd) are provided on the semiconductor layer (12s1).Type: ApplicationFiled: November 10, 2011Publication date: September 12, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Kazuhide Tomiyasu, Tomohiro Kimura
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Patent number: 8492212Abstract: Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.Type: GrantFiled: February 17, 2010Date of Patent: July 23, 2013Assignee: Sharp Kabushiki KaishaInventors: Tokuaki Kuniyoshi, Hidehito Kitakado, Tadayoshi Miyamoto, Kazuhide Tomiyasu, Sumio Katoh
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Patent number: 8421076Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.Type: GrantFiled: September 8, 2008Date of Patent: April 16, 2013Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Shin Matsumoto, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
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Publication number: 20130037816Abstract: A semiconductor device (130) includes: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90) bonded to the bonding substrate (100), the semiconductor element (90) including semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on a side of the semiconductor element main body (50) facing the bonding substrate (100), and each of the underlying layers (51-54) including an insulating layer and a circuit pattern in the insulating layer, wherein an end of the semiconductor element (90) facing the thin film element (80) is provided in a stepped form so that the closer to the bonding substrate the underlying layers arc, the farther ends of the underlying layers facing the thin film element protrude, the end of the semiconductor element (90) is covered with a resin layer (120), and the thin film element (80) is connected to the semiconductor element main body (50) via a connection line (121a) provided on the resinType: ApplicationFiled: December 2, 2010Publication date: February 14, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kenshi Tada, Shin Matsumoto
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Patent number: 8361882Abstract: Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.Type: GrantFiled: August 21, 2009Date of Patent: January 29, 2013Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Shin Matsumoto, Kazuo Nakagawa, Yutaka Takafuji