Patents by Inventor Kazuhide Tomiyasu

Kazuhide Tomiyasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8354329
    Abstract: A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 15, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Masao Moriguchi, Yutaka Takafuji
  • Publication number: 20130009302
    Abstract: A semiconductor device (130) including: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90a) bonded to the bonding substrate (100), the semiconductor element including a semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on a side of the semiconductor element main body facing the bonding substrate (100), wherein the underlying layer (54) closest to the bonding substrate (100) includes an extended section (E) formed by extending the circuit pattern toward the thin film element (80), a resin layer (120) is provided between the thin film element (80) and the semiconductor element (90a), and the thin film element (80) is connected to the semiconductor element main body (50) via a connection line (121a) provided on the resin layer (120), the extended section (E), and the circuit patterns.
    Type: Application
    Filed: December 2, 2010
    Publication date: January 10, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kenshi Tada, Shin Matsumoto
  • Patent number: 8288184
    Abstract: A production method for producing a semiconductor device capable of improving surface flatness and suppressing a variation in electrical characteristics of the semiconductor chip, and improving production yield. The production method includes the steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: October 16, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Steven Roy Droes
  • Publication number: 20120242624
    Abstract: An object of the present invention is to provide a thin film transistor fabricating method including a simplified step of forming contact holes. This method involves previously removing a gate insulating film (115) on a gate electrode (110) which is not covered with a channel layer (120) in a TFT (100). Hence, an insulating film formed on the gate electrode (110) which is not covered with the channel layer (120) becomes equal in thickness to an insulating film formed on a source region (120a) and a drain region (120b). Therefore, a contact hole (155) reaching a surface of the gate electrode (110) can be formed simultaneously with a contact hole (135a) reaching a surface of the source region (120a) and a contact hole (135b) reaching a surface of the drain region (120b).
    Type: Application
    Filed: July 21, 2010
    Publication date: September 27, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Hidehito Kitakado, Tadayoshi Miyamoto
  • Publication number: 20120242923
    Abstract: An active matrix substrate (20a) includes a gate electrode (11aa), a gate insulating layer (12) covering the gate electrode (11aa), an oxide semiconductor layer (13a) provided on the gate insulating layer (12) and having a channel region (C), a source electrode (16aa) and a drain electrode (16b) provided on the oxide semiconductor layer (13a), an interlayer insulating film (17) covering the oxide semiconductor layer (13a), the source electrode (16aa), and the drain electrode (16b), and a planarization film (18) provided on the interlayer insulating film (17). An opening (Ca) reaching the interlayer insulating film (17) is formed at a portion of the planarization film (18) which is located over the channel region (C).
    Type: Application
    Filed: October 28, 2010
    Publication date: September 27, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tadayoshi Miyamoto, Kazuhide Tomiyasu
  • Publication number: 20120200546
    Abstract: Disclosed is a semiconductor device including plural types of semiconductor elements having structures that have respective thicknesses suitable for their uses formed in the same process. A semiconductor device (100) includes a TFT (40) and a photodiode (50). A gate electrode (110) of the TFT (40) and a light-shielding layer (60) of the photodiode (50) are formed in the same process. However, because the film thickness of the gate electrode (110) is small, the breakage of an island-shaped silicon layer (120), which will be the channel layer, at the edge of the gate electrode (110) can be prevented. Also, because the film thickness of the light-shielding layer (60) is large, the light entering through a surface of a glass substrate (101) on the side opposite from the surface on which the TFT is formed can be reliably blocked by the light-shielding layer (60). Consequently, the detection sensitivity of the photodiode (50) can be increased.
    Type: Application
    Filed: June 7, 2010
    Publication date: August 9, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Kazuhide Tomiyasu, Sumio Katoh
  • Patent number: 8232213
    Abstract: A method for manufacturing a semiconductor device includes: a first etching step of etching a TEOS layer from a glass substrate to partially expose a SiN layer; a second etching step, conducted separately and independently from the first etching step, of wet-etching the exposed SiN layer to partially expose the glass substrate; and a bonding step of bonding a driver portion to the exposed glass substrate.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: July 31, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuhide Tomiyasu
  • Patent number: 8188564
    Abstract: A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: May 29, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa
  • Patent number: 8184225
    Abstract: The present invention provides a semiconductor device which can be produced by simple and cheap processes and effectively achieve improved performances and a reduced electric power consumption. Further, the present invention provides a production method thereof and a display device including the semiconductor device or a semiconductor device produced by the production method. The present invention is a semiconductor device including a pixel part and an integrated circuit part on a substrate, the pixel part including a switching element having a gate electrode formed on a semiconductor thin film, the integrated circuit part including a semiconductor layer on a gate electrode, wherein a passivation film is formed on the gate electrode in the pixel part.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: May 22, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuhide Tomiyasu
  • Publication number: 20120115286
    Abstract: Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.
    Type: Application
    Filed: February 17, 2010
    Publication date: May 10, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tokuaki Kuniyoshi, Hidehito Kitakado, Tadayoshi Miyamoto, Kazuhide Tomiyasu, Sumio Katoh
  • Publication number: 20120038022
    Abstract: Disclosed is a glass substrate (20) that is capable of constituting a semiconductor device (10) when a monocrystalline silicon thin film (90) is provided on the surface of the substrate by transfer. The surface of the glass substrate (20) has a receiving surface (22) onto which the monocrystalline silicon thin film (90) can be provided. The height of the ripples on the receiving surface (22) having a period of 200 to 500 microns is no more than 0.40 nm.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 16, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa, Kenshi Tada, Michiko Takei, Shin Matsumoto
  • Patent number: 8101502
    Abstract: A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a height of the planarization assisting layer from a surface of the first planarizing layer located on a side opposite to the substrate layer becomes equal between at least a part of a region where the conductive films are formed, and at least a part of a region where no conductive film is formed.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: January 24, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Kazuhide Tomiyasu, Michiko Takei, Steven Droes
  • Publication number: 20110309467
    Abstract: Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).
    Type: Application
    Filed: November 25, 2009
    Publication date: December 22, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Kenshi Tada
  • Publication number: 20110272694
    Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.
    Type: Application
    Filed: September 8, 2008
    Publication date: November 10, 2011
    Inventors: Michiko Takei, Shin Matsumoto, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20110241174
    Abstract: Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.
    Type: Application
    Filed: August 21, 2009
    Publication date: October 6, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Shin Matsumoto, Kazuo Nakagawa, Yutaka Takafuji
  • Patent number: 8008205
    Abstract: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: August 30, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Michiko Takei, Kazuhide Tomiyasu
  • Patent number: 7989304
    Abstract: A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: August 2, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20110042693
    Abstract: A semiconductor device (10) includes a support substrate (14), an adhered device part (11) adhered to the support substrate (14), a multilayer device part (13) stacked on the adhered device part (11), and an adjacent device part (12) formed in a region adjacent to the adhered device part on the support substrate (14). The adhered device part (11), the multilayer device part (13), and the adjacent device part (12) are electrically connected to one another.
    Type: Application
    Filed: April 9, 2009
    Publication date: February 24, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto
  • Publication number: 20100295105
    Abstract: A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.
    Type: Application
    Filed: September 25, 2008
    Publication date: November 25, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Kazuhide Tomiyasu, Yutaka Takafuji, Kenshi Tada, Michiko Takei
  • Patent number: 7838936
    Abstract: An active matrix substrate includes a glass substrate, a driver portion formed on the glass substrate in a protruding state, a stepped portion formed along a surface of the driver portion and a surface of the glass substrate, an insulating reentrant-angle compensating film formed on a surface of the stepped portion, for compensating for at least a part of a reentrant-angle shape of the stepped portion, and a wiring layer formed along a surface of the reentrant-angle compensating film and connected to the driver portion.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: November 23, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Masao Moriguchi