Patents by Inventor Kazuhiko Yoshida

Kazuhiko Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110107037
    Abstract: According to one embodiment, an information processing apparatus includes memory modules, a measuring module, a determination module, and a controller. The measuring module initializes the memory modules when the apparatus has been booted and an operating system of the information processing apparatus has not yet been started, measures a temperature of the memory modules at a time of the initialization, and measures a maximum temperature of each of the memory modules when the operating system is running. The determination module determines a first memory module, which has the least difference between the temperature at the time of the initialization and the maximum temperature at the time when the operating system is running, and a second memory module which has the lowest temperature at the time of the initialization. The controller maps memory addresses allocated to the first memory module in the second memory module, based on the temperatures.
    Type: Application
    Filed: July 28, 2010
    Publication date: May 5, 2011
    Inventor: Kazuhiko Yoshida
  • Patent number: 7910455
    Abstract: The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of either the base wafer or the bond wafer at a dosage of 1×1015 atoms/cm2 or more at least before the bonding step, the surface ion-implanted with argon is used as a bonding surface in the bonding step, and an increase rate of temperature to a treatment temperature of the bonding heat treatment is 5° C./minute or higher. Thus the present invention provides a method for producing an SOI wafer facilitating the efficient production of an SOI wafer having in the neighborhood of a buried insulator layer thereof a polycrystalline silicon layer uniform in thickness introduced and having high gettering ability toward metal contaminations in the SOI layer by a simple and low-cost method.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: March 22, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
  • Patent number: 7912417
    Abstract: An image forming apparatus includes: an image forming part; a first conveyance roller that conveys a recording medium to the image forming part; a forward/reverse-rotatable second conveyance roller, located between the first conveyance roller and the image forming part in a conveyance direction of the recording medium; a contact member, in contact with the second conveyance roller, that forms a nip between the second conveyance roller and the contact member; a first conveyance roller driver that rotate-drives the first conveyance roller in the same direction as the conveyance direction of the recording medium; and a drive transmission mechanism that performs drive transmission from the first conveyance roller driver to the second conveyance roller so as to start rotation of the second conveyance roller in a reverse direction of the conveyance direction of the recording medium before a lead edge of the recording medium arrives at the nip.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 22, 2011
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Kazuhiko Yoshida
  • Publication number: 20110065519
    Abstract: Provided is a fixed type constant velocity universal joint of an eight-ball undercut-free type, which is capable of achieving an improvement of torque capacity at a high operating angle while ensuring durability at the time of a low operating angle. In the fixed type constant velocity universal joint of the eight-ball undercut-free type, a center of a track groove (32) of an outer joint member and a center of a track groove (35) of an inner joint member are separated from a joint center plane (P) respectively to both sides in an axial direction, and are offset to be positioned away from a joint center axis (X) to a radially opposite side relative to the track grooves (35). When Rt represents a distance between a center of a ball (37) and the center of the track groove (32) of the outer joint member, and F represents an axial distance between the joint center plane (P) and the center of the track groove (32) of the outer joint member, a ratio R1 between F and Rt is set to satisfy 0.061?R1?0.
    Type: Application
    Filed: May 28, 2009
    Publication date: March 17, 2011
    Inventors: Keisuke Sone, Hirokazu Ooba, Kazuhiko Yoshida, Kiyohiro Itou
  • Publication number: 20110003645
    Abstract: Provided is a constant velocity universal joint having high strength and capable of suppressing deformation caused by quenching at an opening end portion of a track groove of an outer joint member. In an undercut-free constant velocity universal joint in which a track groove (1d) in a cup portion (1a) of the outer joint member has a hardened layer (8a) formed by induction quenching, an opening end surface (1e) is protruded by a protruding amount t in an axial direction from a groove bottom (c) of the track groove (1d) in a relief surface (1f). The protruding amount t satisfies a relation of t=0.037 d to 0.185 d when a diameter of a torque transmission ball is represented by d. The opening end surface (1e) in a protruded portion (1i) and an outer surface (1j) of the cup portion (1a) continuous to the opening end surface (1e) have an unhardened layer free from hardening by quenching.
    Type: Application
    Filed: September 22, 2008
    Publication date: January 6, 2011
    Inventors: Hirokazu Ooba, Kazuhiko Yoshida, Keisuke Sone
  • Publication number: 20100323803
    Abstract: The present invention provides a constant velocity universal joint component and a manufacturing method thereof capable of achieving increased strength without significant procedural changes, and that can contribute to size reduction and weight reduction. In the constant velocity universal joint component of the present invention, a sharp-angled portion 15 is formed by machining after cold plastic working is applied. A carburization process is then performed in which surface carbon concentration of 0.45 mass % to less than 0.60 mass % is obtained. Quenching is then performed. High-frequency induction hardening is subsequently performed.
    Type: Application
    Filed: January 28, 2008
    Publication date: December 23, 2010
    Inventor: Kazuhiko Yoshida
  • Patent number: 7824106
    Abstract: A bearing device for a wheel enabling the easy control of quality since there is no possibility of cracking even if caulking is applied thereto. The bearing device comprises an outer ring having double rows of raceway surfaces on the inner periphery thereof, an inner member having raceway surfaces opposed to the raceway surfaces, and balls interposed between the double rows of raceway surfaces opposed to each other. The inner member further comprises a HUB ring and an inner ring. Caulking is applied to the HUB ring to join it to the inner ring. The grain size number of the austenite grains of a caulked section is at least 6.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: November 2, 2010
    Assignee: NTN Corporation
    Inventors: Isao Hirai, Takayasu Takubo, Kazuhiko Yoshida
  • Publication number: 20100264510
    Abstract: In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.
    Type: Application
    Filed: October 20, 2008
    Publication date: October 21, 2010
    Applicants: DENSO CORPORATION, Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Ohtsuki, Mitsutaka Katada, Nobuhiko Noto, Hiroshi Takeno, Kazuhiko Yoshida
  • Publication number: 20100234115
    Abstract: The present invention provides a compact constant velocity universal joint having high strength, and superior operability and durability. In the constant velocity universal joint of the present invention, an offset angle øT formed by a center of curvature OT0 of a guiding groove 2b of an outer component 2, an intersecting point Q between a joint plane P and a PCD, and a center of curvature OT1 of a guiding groove 3b of an inner component 3 is set to 11.0°?øT?15.0°.
    Type: Application
    Filed: April 27, 2007
    Publication date: September 16, 2010
    Inventors: Kazuhiko Yoshida, Masazumi Kobayashi, Kazuhiro Azuma
  • Publication number: 20100209285
    Abstract: A magnesium alloy for casting according to the present invention is characterized in that, when the entirety is taken as 100% by mass, it includes copper (Cu) in an amount of from 1% by mass or more to 5% by mass or less, calcium (Ca) in an amount of from 0.1% by mass or more to 5% by mass or less, tin (Sn) in an amount of from 0.1 or more to 3 or less by mass ratio with respect to the Ca (Sn/Ca); and the balance comprising magnesium (Mg) and inevitable impurities. By means of including Cu, Ca and Sn, crystallized substances of Mg—Ca—Sn compounds crystallize in crystalline grain boundaries between Mg crystalline grains as network shapes (three-dimensionally mesh shapes), along with Mg—Cu compounds. By means of the three-dimensionally mesh constructions, grain-boundary sliding, which becomes active especially when becoming high temperature, is suppressed, and thereby high-temperature strength and creep resistance at high temperature improve.
    Type: Application
    Filed: April 14, 2008
    Publication date: August 19, 2010
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yuki Okamoto, Kyoichi Kinoshita, Motoharu Tanizawa, Kazuhiko Yoshida
  • Patent number: 7776453
    Abstract: A hub ring and/or an outer ring constituting a bearing device for a wheel, which is formed of a steel which contains 0.45 to 0.70 mass % of C and at least one of V, Nb and Ti in a total amount of 0.3 mass % or less, wherein a micro structure of a part being not surface-hardening-treated contains a ferrite in 15 to 30 area % and contains a particulate ferrite.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: August 17, 2010
    Assignee: NTN Corporation
    Inventors: Isao Hirai, Takayasu Takubo, Kazuhiko Yoshida
  • Publication number: 20100184923
    Abstract: An epoxy resin composition comprising, containing a solid epoxy resin (A) whose aromatic ring containing ratio is 5-40% obtained by reacting a polyester compound (b) possessing 1.2-1.8 of carboxylic group with a divalent epoxy resin (a) whose epoxy equivalent is 120-350 g/eq and a crosslinking agent (B) as essential components, and since a cured product obtained by curing said composition is superior in heat resistance, humid resistance and cracking resistance, said composition is useful in a field of electron material such as photo semi conductor sealing material, in particular useful for LED sealing.
    Type: Application
    Filed: June 12, 2008
    Publication date: July 22, 2010
    Inventors: Kazuhiko Yoshida, Masao Gunji, Seigou Takuwa
  • Patent number: 7727426
    Abstract: Disclosed is an epoxy resin composition which is solid at ordinary room temperature, cures with excellent light resistance and heat resistance and minimal shrinkage, and is useful for encapsulating LEDs. The epoxy resin composition is characterized by comprising as an essential component an epoxy resin having an epoxy equivalent of 300-1000 g/eq and a softening point of 65-110° C. obtained by reacting a nonaromatic polycarboxylic acid (A) having an acid value of 100-250 mgKOH/g with a nonaromatic epoxy resin (B) having an epoxy equivalent of 100-400 g/eq. The nonaromatic polycarboxylic acid (A) may be obtained by reacting 1,4-cyclohexanedimethanol, 2,2-bis(4-hydroxycyclohexyl)propane, or 3,9-bis(1,1-dimethyl-2-hydroxyethyl)-2,4,8,10-tetraoxaspiro[5,5]undecane with methylhexahydrophthalic acid or hexahydrophthalic acid.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: June 1, 2010
    Assignee: Nippon Steel Chemical Co., Ltd.
    Inventors: Kazumasa Kobayashi, Chiaki Asano, Hiroshi Sato, Yasuyuki Takeda, Kazuhiko Yoshida
  • Publication number: 20100119405
    Abstract: A magnesium alloy for casting according to the present invention is characterized in that, when the entirety is taken as 100% by mass, it includes copper (Cu) in an amount of from 1% by mass or more to 5% by mass or less, calcium (Ca) in an amount of from 0.1% by mass or more to 5% by mass or less, silver (Ag) in an amount of from 0.1% by mass or more to 5% by mass or less, and the balance comprising magnesium (Mg) and inevitable impurities. By means of including Cu and Ca, crystallized substances of Mg—Ca compounds crystallize in crystalline grain boundaries between Mg crystalline grains as three-dimensionally mesh shapes, along with Mg—Cu compounds. By means of the three-dimensionally mesh constructions, grain-boundary sliding, which becomes active especially when becoming high temperature, is suppressed, and thereby high-temperature strength and creep resistance at high temperature improve.
    Type: Application
    Filed: April 14, 2008
    Publication date: May 13, 2010
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yuki Okamoto, Kyoichi Kinoshita, Motoharu Tanizawa, Kazuhiko Yoshida
  • Publication number: 20100022038
    Abstract: The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of a semiconductor as an evaluation target through the windows at the two positions and forming diffused portions in the semiconductor as the evaluation target to form PN junctions; and performing leakage current measurement and/or DLTS measurement in a part between the two diffused portions to evaluate the semiconductor wafer. As a result, there is provided the method for evaluating a semiconductor wafer that can perform junction leakage current measurement or DLTS measurement to easily evaluate a quality of the inside of the semiconductor wafer. In particular, there can be provided the method that can evaluate not only a PW or an EPW but also the inside of an SOI layer of an SOI wafer.
    Type: Application
    Filed: October 18, 2007
    Publication date: January 28, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Tsuyoshi Ohtsuki, Kazuhiko Yoshida
  • Publication number: 20100019271
    Abstract: The present invention relates to an epoxy resin composition for optical semiconductor element encapsulation, the epoxy resin composition including following components (A) to (C): (A) an epoxy resin represented by the following structural formula (1): in which n is a positive number, (B) an epoxy resin except for the epoxy resin represented by the structural formula (1), and (C) a curing agent.
    Type: Application
    Filed: July 27, 2009
    Publication date: January 28, 2010
    Applicant: NITTO DENKO CORPORATION
    Inventors: Shinya OTA, Kazuhiro FUKE, Chisato GOTO, Hisataka ITO, Takashi TANIGUCHI, Kazuhiko YOSHIDA, Masao GUNJI, Seigou TAKUWA
  • Publication number: 20100016086
    Abstract: In the fixed type constant velocity universal joint, the center of each of the guide grooves of the outer joint member is offset to a position of being spaced apart from the joint central plane to the joint opening side by an axial distance (F), and being spaced apart from the joint central axis line to an opposite side in a radial direction with respect to each of the guide grooves by a radial distance (Fr). Further, the center of each of the guide grooves of the inner joint member is offset to a position of being spaced apart from the joint central plane to a joint innermost side by the axial distance (F), and being spaced apart from the joint central axis line to the opposite side in the radial direction with respect to each of the guide grooves by the radial distance (Fr).
    Type: Application
    Filed: December 5, 2007
    Publication date: January 21, 2010
    Inventors: Keisuke Sone, Kazuhiko Yoshida, Hirokazu Ooba
  • Publication number: 20090280620
    Abstract: The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.
    Type: Application
    Filed: April 23, 2007
    Publication date: November 12, 2009
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
  • Patent number: 7607656
    Abstract: An image forming apparatus includes: an image forming part; a sheet container that contains sheets fed to the image forming part in a stacked state; a feed roller that feeds the sheet from the sheet container; a separation member in press-contact with the feed roller that separates the sheet at a contact point formed between the feed roller and the separation member; and a press-contact force reducing unit that reduces a press contact force of the separation member to the feed roller while maintaining an approximately constant sheet separating force with the separation member.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: October 27, 2009
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Kazuhiko Yoshida
  • Publication number: 20090251135
    Abstract: The present invention relates to a method for evaluating the SOI wafer in a method for evaluating an SOI wafer in which a sheet resistance of a buried diffusion layer of an SOI wafer that has at least an SOI layer on an insulator layer and has a buried diffusion layer whose impurity concentration is higher than other region of the SOI layer in an interface area with the insulator layer of the SOI layer is evaluated, the method including the steps of measuring a sheet resistance of the whole SOI layer or the whole SOI wafer, and estimating the sheet resistance of the buried diffusion layer by assuming respective layers that compose the SOI wafer to be resistors connected in parallel and converting the measured result of the sheet resistance measurement. As a result of this, there is provided a method for evaluating the SOI wafer that can directly measure the SOI wafer itself to be the product to thereby evaluate the sheet resistance of the buried diffusion layer thereof, without fabricating a monitor wafer.
    Type: Application
    Filed: May 10, 2007
    Publication date: October 8, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventor: Kazuhiko Yoshida