Abstract: A redox flow battery system includes pumps, a pump control unit, an SQC measuring unit, and a terminal-voltage measuring unit. The pump control unit includes a reference-flow-rate acquiring unit which acquires a reference flow rate of the pumps corresponding to the state of charge of electrolytes; a terminal-voltage determination unit which determines whether or not a terminal voltage of a battery cell reaches the lower limit or the ripper limit of a predetermined voltage range; and a pump-flow-rate setting unit which sets the reference flow rate for the pumps in the case where the terminal voltage does not reach the upper or lower limit of the predetermined voltage range, and sets a flow rate obtained by adding a predetermined flow rate to the reference flow rate for the pumps in the ease where the terminal voltage reaches the upper or lower limit of the predetermined voltage range.

Abstract: A power conversion apparatus 1 according to an embodiment of the present invention includes a high-voltage side input terminal TIH and a low-voltage side input terminal TIL, first and second output terminals TO1 and TO2, a power conversion circuit 10 that converts direct-current power input between the high-voltage side input terminal TIH and the low-voltage side input terminal TIL to generate alternating-current power between the first and second output terminals TO1 and TO2, and an inverted-voltage generation circuit 30 that generates an inverted voltage of a common mode voltage generated between the first and second output terminals TO1 and TO2 and inputs the inverted voltage to the low-voltage side input terminal TIL.

Abstract: A redox flow battery system includes pumps which circulate and supply electrolytes to a battery cell, a pump control unit which controls the flow rate of the pumps, an SOC measuring unit which measures the state of charge of the electrolytes, and a terminal-voltage measuring unit which measures a terminal voltage of the battery cell.

Abstract: Provided are a redox flow battery system and a method for operating a redox flow battery that suppress overcharge and overdischarge of an electrolyte. A redox flow battery system includes a pump that supplies an electrolyte to a battery cell by circulation, a pump controller that controls a flow rate of the pump, and a measurement unit that measures at least two parameters selected from among an inlet-side state of charge of the electrolyte supplied to the battery cell, an outlet-side state of charge of the electrolyte drained from the battery cell, and a charge/discharge current input to/output from the battery cell. The pump controller includes a pump flow-rate computation unit that calculates a charge/discharge efficiency of the battery cell from the parameters measured by the measurement unit and, based on the charge/discharge efficiency, determines the flow rate of the pump so that the electrolyte drained from the battery cell is neither overcharged nor overdischarged.

Abstract: A power conversion apparatus 1 according to an embodiment of the present invention includes a high-voltage side input terminal TIH and a low-voltage side input terminal TIL, first and second output terminals TO1 and TO2, a power conversion circuit 10 that converts direct-current power input between the high-voltage side input terminal TIH and the low-voltage side input terminal TIL to generate alternating-current power between the first and second output terminals TO1 and TO2, and an inverted-voltage generation circuit 30 that generates an inverted voltage of a common mode voltage generated between the first and second output terminals TO1 and TO2 and inputs the inverted voltage to the low-voltage side input terminal TIL.

Abstract: A power inverter circuit 1 is a bridge power inverter circuit comprising first and second switching elements 11, 12 sequentially connected in series between input terminals on higher and lower voltage sides and third and fourth switching elements 13, 14 sequentially connected in series between the input terminals on the higher and lower voltage sides and alternately turning on a set of the first and fourth switching elements 11, 14 and a set of the second and third switching elements 12, 14 so as to convert a DC power fed between the input terminals on the higher and lower voltage sides into an AC power. One of the sets of the first and third switching elements 11, 13 and the second and fourth switching elements 12, 14 is subjected to switching control at a frequency higher than that of the other.

Abstract: The stacked battery includes a negative electrode (46) and a positive electrode (41). The negative electrode has a negative electrode main portion (50) and a negative electrode lead (52). The positive electrode has a positive electrode main portion (45) and a positive electrode lead (51). The negative electrode main portion and the positive electrode main portion are stacked in a thickness direction with the negative electrode lead and the positive electrode lead extending in different directions as viewed from above. The positive electrode lead is fixed to a positive electrode case. In the positive electrode lead, a break place (X) is provided outside the negative electrode main portion as viewed from above when the negative electrode and the positive electrode are placed on top of each other. The break place (X) is broken when a shock is applied to the electrodes.

Abstract: Provided is a transistor protection circuit capable of appropriately protecting a transistor even when a switching frequency is high. A transistor protection circuit according to an embodiment of the present invention is a transistor protection circuit for protecting a voltage-driven transistor that is switch-controlled by the application of a high-potential-side voltage or low-potential-side voltage of a power supply to a gate terminal of the transistor by a drive circuit. The transistor protection circuit has a power supply controller that gradually lowers the high-potential-side voltage of the power supply upon receiving a protection command for executing protection of the transistor.

Abstract: A switching circuit 33 comprises a connection circuit cascade-connecting control terminals for controlling switching of n number of transistors M1-Mn via n?1 number of coils L1 respectively (n is an integer equal to or more than 2; and coils L3 respectively connected between one end of each of the transistors M1-Mn and other end of a coil L2, one end of the coil L2 being electrically connected to a DC power source. The transistors M1-Mn is sequentially switched with PWM signals inputted to an input terminal of the connection circuit. The switching circuit 33 further comprises a transistor M0 inserted at the one end or the other end of the coil L2 in cascade-connection.

Abstract: A switching circuit according to one embodiment has: N switching elements; a connection circuit including N?1 first inductance elements that are connected in series; a second inductance element; and N third inductance elements. Control terminals of the N switching elements are connected to ends of the connection circuit and connection contacts, respectively. One end of the second inductance element is connected to a power supply. The N third inductance elements electrically connects one ends of the N switching elements and the other end of the second inductance element with each other, respectively.

Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.

Abstract: A semiconductor module in accordance with one embodiment comprises a plurality of semiconductor switching devices; a plurality of control circuits provided for the respective semiconductor switching devices and adapted to control switching of the semiconductor switching devices corresponding thereto and perform protection actions to stop switching the semiconductor switching devices corresponding thereto falling into a control stop state; and a signal path connecting the plurality of control circuits to each other and transmitting among the plurality of control circuits a protection action signal indicating whether or not there is the protection action for each of the semiconductor switching devices corresponding to the plurality of control circuits. Any of the plurality of control circuits receiving the protection action signal indicating that another control circuit is in the protection action through the signal path stops switching the semiconductor switching device corresponding thereto.

Abstract: A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

Abstract: A lateral field-effect transistor capable of improving switching speed and reducing operationally defective products is provided. A gate wiring has a base, a plurality of fingers protruding from the base, and a connection connecting tips of adjacent fingers. The finger of the gate wiring is arranged between the finger of a source wiring and the finger of a drain wiring. The base of the gate wiring is arranged between the base of the source wiring and the fingers of the drain wiring and intersects with the fingers of the source wiring, with an insulating film interposed between the base of the gate wiring and the fingers.

Abstract: An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.

Abstract: A power inverter circuit 1 is a bridge power inverter circuit comprising first and second switching elements 11, 12 sequentially connected in series between input terminals on higher and lower voltage sides and third and fourth switching elements 13, 14 sequentially connected in series between the input terminals on the higher and lower voltage sides and alternately turning on a set of the first and fourth switching elements 11, 14 and a set of the second and third switching elements 12, 14 so as to convert a DC power fed between the input terminals on the higher and lower voltage sides into an AC power. One of the sets of the first and third switching elements 11, 13 and the second and fourth switching elements 12, 14 is subjected to switching control at a frequency higher than that of the other.

Abstract: The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.

Abstract: A switching circuit 1 comprises a transistor 11; a detection resistance 12, connected to the transistor 11, for receiving a current flowing through the transistor 11; an overcurrent detection circuit 13 for detecting from a voltage between both ends of the detection resistance 12 whether or not the current flowing through the transistor 11 is an overcurrent; a control circuit 15 for switching control of the transistor 11, the control circuit restricting the switching control when the overcurrent detection circuit 13 detects that the current flowing through the transistor 11 is the overcurrent; and a level-shift circuit 14, disposed between the overcurrent detection circuit 13 and the control circuit 15, for level-shifting a signal from the overcurrent detection circuit 13 and transmitting the level-shifted signal to the control circuit 15; the overcurrent detection circuit 13 having a ground potential different from that of the control circuit 15.