Patents by Inventor Kazuhiro Fujikawa
Kazuhiro Fujikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7671388Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: September 1, 2009Date of Patent: March 2, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7671387Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: July 24, 2008Date of Patent: March 2, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20100044721Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.Type: ApplicationFiled: August 21, 2008Publication date: February 25, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kazuhiro Fujikawa, Shin Harada, Yasuo Namikawa, Takeyoshi Masuda
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Publication number: 20100035411Abstract: A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.Type: ApplicationFiled: August 13, 2007Publication date: February 11, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kazuhiro Fujikawa, Takeyoshi Masuda
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Publication number: 20100035420Abstract: A method of manufacturing a semiconductor device includes a first step of forming an ion implantation mask on a portion of a surface of a semiconductor; a second step of implanting ions of a first dopant into at least a portion of an exposed region of the surface of the semiconductor other than the region where the ion implantation mask is formed, to form a first dopant implantation region; a third step of, after forming the first dopant implantation region, removing a portion of the ion implantation mask to increase the exposed region of the surface of the semiconductor; and a fourth step of implanting ions of a second dopant into at least a portion of the increased exposed region of the surface of the semiconductor to form a second dopant implantation region.Type: ApplicationFiled: November 29, 2007Publication date: February 11, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hideto Tamaso, Kazuhiro Fujikawa, Shin Harada
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Publication number: 20090315082Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: ApplicationFiled: September 1, 2009Publication date: December 24, 2009Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20090154210Abstract: The present invention provides a bi-directional field effect transistor and a matrix converter using the same, in which a current flowing bi-directionally can be controlled by means of a single device. The bi-directional field effect transistor includes: a semiconductor substrate 1; a gate region which is arranged on the semiconductor substrate 1, with a channel parallel to a principal surface of the substrate 1 and a gate electrode 13a for controlling conductance of the channel; a first region which is arranged on a first side of the channel; and a second region which is arranged on a second side of the channel; wherein a forward current which flows from a first electrode 11a of the first region through the channel to a second electrode 12a of the second region and a backward current which flows from the second electrode 12a through the channel to the first electrode 11a can be controlled by a gate voltage applied to the gate electrode 13a.Type: ApplicationFiled: September 30, 2005Publication date: June 18, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Kazuhiro Fujikawa
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Publication number: 20090152566Abstract: A junction field-effect transistor comprises an n-type semiconductor layer having a channel region, a buffer layer formed on the channel region and a p+ region formed on the buffer layer. The concentration of electrons in the buffer layer is lower than the concentration of electrons in the semiconductor layer. The concentration of electrons in the buffer layer is preferably not more than one tenth of the concentration of electrons in the semiconductor layer. Thus, the threshold voltage can be easily controlled, and saturation current density of a channel can be easily controlled.Type: ApplicationFiled: September 8, 2005Publication date: June 18, 2009Inventors: Kazuhiro Fujikawa, Shin Harada
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Publication number: 20090124091Abstract: The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.Type: ApplicationFiled: January 12, 2009Publication date: May 14, 2009Applicants: Kanto Kagaku Kabushiki Kaisha, Sanyo Electric Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd.Inventors: Kazuhiro Fujikawa, Tsuguhiro Tago
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Publication number: 20080277696Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: ApplicationFiled: July 24, 2008Publication date: November 13, 2008Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20080254603Abstract: There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO2 film and a thin metal film; and introducing dopant ions.Type: ApplicationFiled: March 20, 2008Publication date: October 16, 2008Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada
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Patent number: 7420232Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: April 11, 2006Date of Patent: September 2, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7364978Abstract: There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO2 film and a thin metal film; and introducing dopant ions.Type: GrantFiled: April 20, 2004Date of Patent: April 29, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada
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Patent number: 7321142Abstract: On an SiC single crystal substrate, an electric field relaxation layer and a p? type buffer layer are formed. The electric field relaxation layer is formed between the p? type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p? type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.Type: GrantFiled: May 21, 2004Date of Patent: January 22, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20070278540Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.Type: ApplicationFiled: June 28, 2007Publication date: December 6, 2007Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takashi Hoshino, Shin Harada, Kazuhiro Fujikawa, Satoshi Hatsukawa, Kenichi Hirotsu
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Patent number: 7282760Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.Type: GrantFiled: July 24, 2003Date of Patent: October 16, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Hoshino, Shin Harada, Kazuhiro Fujikawa, Satoshi Hatsukawa, Kenichi Hirotsu
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Publication number: 20060202238Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: ApplicationFiled: April 11, 2006Publication date: September 14, 2006Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20060113574Abstract: On an SiC single crystal substrate, an electric field relaxation layer and a p? type buffer layer are formed. The electric field relaxation layer is formed between the p? type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p? type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.Type: ApplicationFiled: May 21, 2004Publication date: June 1, 2006Inventors: Kazuhiro Fujikawa, Shin Harada, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7049644Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: December 2, 2002Date of Patent: May 23, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20060063342Abstract: There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO2 film and a thin metal film; and introducing dopant ions.Type: ApplicationFiled: April 20, 2004Publication date: March 23, 2006Inventors: Kazuhiro Fujikawa, Shin Harada