Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.

Abstract: The stacked battery includes a negative electrode (46) and a positive electrode (41). The negative electrode has a negative electrode main portion (50) and a negative electrode lead (52). The positive electrode has a positive electrode main portion (45) and a positive electrode lead (51). In the negative electrode and the positive electrode, the negative electrode main portion and the positive electrode main portion are stacked in a thickness direction with the negative electrode lead and the positive electrode lead extending in different directions as viewed from above. The positive electrode lead is fixed to a positive electrode case. In the positive electrode lead, a break place (X) is provided outside the negative electrode main portion as viewed from above when the negative electrode and the positive electrode are placed on top of each other. The break place (X) is broken when a shock is applied to the electrodes.

Abstract: A switching circuit according to one embodiment has: N switching elements; a connection circuit including N?1 first inductance elements that are connected in series; a second inductance element; and N third inductance elements. Control terminals of the N switching elements are connected to ends of the connection circuit and connection contacts, respectively. One end of the second inductance element is connected to a power supply. The N third inductance elements electrically connects one ends of the N switching elements and the other end of the second inductance element with each other, respectively.

Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.

Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: Substrates are mounted on a plurality of susceptors respectively. The plurality of susceptors on which respective substrates are mounted are placed on a rotational mechanism so that the susceptors are vertically spaced at a predetermined interval. The rotational mechanism on which the plurality of susceptors are placed is rotated. The plurality of susceptors on which the substrates are mounted respectively are heated. Semiconductor thin-films are deposited by supplying a source gas to each of the susceptors that are heated while being rotated, the source gas having been heated while passing through gas flow paths of respective path lengths substantially equal to each other.

Abstract: A buffer layer is provided on a substrate, is made of silicon carbide containing an impurity, and has a thickness larger than 1 ?m and smaller than 7 ?m. A drift layer is provided on the buffer layer and is made of silicon carbide having an impurity concentration smaller than that of the buffer layer. In this way, there can be provided a silicon carbide semiconductor device having the drift layer having a desired impurity concentration and a high crystallinity.

Abstract: A silicon carbide semiconductor device is provided which has a lower on-resistance and a higher breakdown voltage than those of a conventional silicon carbide semiconductor device. A JFET includes an n type substrate, a p type layer, an n type layer, a source region, a drain region, and a gate region. The n type substrate has a main surface having an off angle of not less than 32° relative to the {0001} plane, and is made of silicon carbide (SiC). The p type layer is formed on the main surface of the n type substrate, and has p type conductivity. The n type layer is formed on the p type layer, and has n type conductivity. The source region and the drain region are formed in n type layer with a space interposed therebetween. The gate region is formed in the n type layer at a region between the source region and the drain region.

Abstract: A lateral field-effect transistor capable of improving switching speed and reducing operationally defective products is provided. A gate wiring has a base, a plurality of fingers protruding from the base, and a connection connecting tips of adjacent fingers. The finger of the gate wiring is arranged between the finger of a source wiring and the finger of a drain wiring. The base of the gate wiring is arranged between the base of the source wiring and the fingers of the drain wiring and intersects with the fingers of the source wiring, with an insulating film interposed between the base of the gate wiring and the fingers.

Abstract: A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer.

Abstract: A junction field-effect transistor (20) comprises an n-type semiconductor layer (1) having a channel region, a buffer layer (3) formed on the channel region and a p+ region (4a, 4b) formed on the buffer layer (3). The concentration of electrons in the buffer layer (3) is lower than the concentration of electrons in the semiconductor layer (1). The concentration of electrons in the buffer layer (3) is preferably not more than one tenth of the concentration of electrons in the semiconductor layer (1). Thus, the threshold voltage can be easily controlled, and saturation current density of a channel can be easily controlled.

Abstract: There is provided a method of manufacturing a silicon carbide semiconductor device including the steps of: in a semiconductor stacked substrate including a first conductivity type silicon carbide crystal substrate, a first conductivity type silicon carbide crystal layer, a second conductivity type silicon carbide crystal layer, and a first conductivity type semiconductor region, forming a trench extending through the first conductivity type semiconductor region and the second conductivity type silicon carbide crystal layer into the first conductivity type silicon carbide crystal layer defined as a bottom surface; forming a silicon film on at least a part of the trench; heating the semiconductor stacked substrate having the silicon film formed to a temperature that is not less than the melting temperature of the silicon film; removing the heated silicon film; forming a gate insulating film on a surface exposed after the silicon film is removed; and forming a gate electrode layer on a surface of the gate insula

Abstract: A lateral junction field-effect transistor capable of preventing the occurrence of leakage current and realizing a sufficient withstand voltage can be provided. In a lateral JFET according to the present invention, a buffer layer is located on a main surface of a SiC substrate and includes a p-type impurity. A channel layer is located on the buffer layer and includes an n-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. A source region and a drain region are of n-type and formed to be spaced from each other in a surface layer of the channel layer, and a p-type gate region is located in the surface layer of the channel layer and between the source region and the drain region. A barrier region is located in an interface region between the channel layer and the buffer layer and in a region located under the gate region and includes a p-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer.

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.

Abstract: There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO2 film and a thin metal film; and introducing dopant ions.

Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

Abstract: A substrate composed of hexagonally crystalline SiC is prepared such that its main surface is in the direction at which the minimum angle between the main surface and a plane perpendicular to the (0001) plane is one degree or less, for example, in the direction at which the minimum angle between the main surface and the [0001] direction, which is perpendicular to the (0001) plane, is one degree or less. A horizontal semiconductor device is formed on one main surface of the substrate prepared by the foregoing method. Thus, it was possible to improve the value of breakdown voltage significantly over the horizontal semiconductor device in which the main surface of the substrate composed of hexagonally crystalline SiC is in the direction along the (0001) direction.

Abstract: An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.

Abstract: There is provided a method of manufacturing a silicon carbide semiconductor device including the steps of: in a semiconductor stacked substrate including a first conductivity type silicon carbide crystal substrate, a first conductivity type silicon carbide crystal layer, a second conductivity type silicon carbide crystal layer, and a first conductivity type semiconductor region, forming a trench extending through the first conductivity type semiconductor region and the second conductivity type silicon carbide crystal layer into the first conductivity type silicon carbide crystal layer defined as a bottom surface; forming a silicon film on at least a part of the trench; heating the semiconductor stacked substrate having the silicon film formed to a temperature that is not less than the melting temperature of the silicon film; removing the heated silicon film; forming a gate insulating film on a surface exposed after the silicon film is removed; and forming a gate electrode layer on a surface of the gate insula