Patents by Inventor Kazuhiro Maeda
Kazuhiro Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7523951Abstract: A wheel suspension arm mounting structure of a vehicle in which a suspension arm is mounted to a vehicle body frame member so as to freely swing upward and downward. The wheel suspension arm mounting structure includes a suspension arm support shaft provided on a base of the suspension arm so as to rotate relatively with respect to the suspension arm, a mounting boss provided on the suspension arm support shaft, and a bolt insertion hole provided on the mounting boss. The bolt insertion hole is formed so that a bolt can be inserted in the direction perpendicular to an axis of the suspension arm support shaft, such that the suspension arm support shaft is fixed to an arm mounting portion provided on the vehicle body frame member by the bolt inserted into the insertion hole.Type: GrantFiled: July 18, 2006Date of Patent: April 28, 2009Assignee: Kawasaki Jukogyo KaishaInventors: Sosuke Kinouchi, Kazuhiro Maeda
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Publication number: 20090066897Abstract: In a liquid crystal display including a liquid crystal display panel formed by sandwiching a liquid crystal layer between an active matrix substrate and an opposed substrate, and a backlight that illuminates the liquid crystal display panel from a side of the active matrix substrate, a first optical sensor and a second optical sensor are disposed in a peripheral region on a glass substrate of the active matrix substrate. The first optical sensor is formed so that light external to the liquid crystal display and light propagating inside the active matrix substrate enter the first optical sensor. The second optical sensor is formed so that only light propagating inside the active matrix substrate enters the second optical sensor. Also, the second optical sensor is shielded from the external light. For example, a light-shielding film is formed on an upper surface of the second optical sensor.Type: ApplicationFiled: March 31, 2006Publication date: March 12, 2009Inventors: Hiromi Katoh, Yoshihiro Izumi, Kazuhiro Maeda
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Publication number: 20090051392Abstract: In one embodiment, a circuit device that performs a certain processing operation with respect to an input signal by referring to a reference voltage and outputs the result is caused to have a function of switching the reference voltage, whereby a circuit device from which a stable output can be obtained is disclosed. The circuit device includes a comparator and a reference voltage setting circuit. The comparator compares an input voltage fed from outside with a reference voltage selected from a reference voltage set including a plurality of voltage values that are different from one another.Type: ApplicationFiled: April 20, 2006Publication date: February 26, 2009Inventors: Kazuhiro Maeda, Hiroshi Murofushi, Nobuhiko Suzuki
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Publication number: 20090051678Abstract: A readily-mountable low-cost active matrix display apparatus with a setup function is provided. A serial interface circuit 20 and setup circuits 16 are each formed of TFT elements on a liquid crystal panel 11. The serial interface circuit 20 performs serial-parallel conversion on a setup control signal 17 serially inputted via setup terminals 15. The setup circuits 16 change the states of signals flowing in the liquid crystal panel 11 in accordance with signals outputted in parallel from the serial interface circuit 20. Thus, it is possible to change the potential, timing, etc., of signals inputted to or outputted from any peripheral circuits formed on the liquid crystal panel 11 or any peripheral circuits included in a semiconductor chip mounted on the surface of the liquid crystal panel 11.Type: ApplicationFiled: April 3, 2006Publication date: February 26, 2009Inventors: Masakazu Satoh, Tomoyuki Nagai, Kazuhiro Maeda, Tamotsu Sakai, Shuji Nishi
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Publication number: 20090009374Abstract: A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n?1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.Type: ApplicationFiled: January 11, 2006Publication date: January 8, 2009Inventors: Yasushi Kubota, Kazuhiro Maeda, Hajime Washio, Patrick Zebedee
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Patent number: 7460099Abstract: A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts.Type: GrantFiled: September 23, 2004Date of Patent: December 2, 2008Assignee: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Ichiro Shiraki, Kazuhiro Maeda, Yasuyoshi Kaise
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Patent number: 7414607Abstract: In a structure in which a plurality of signals related to each other are supplied to a driving circuit in such a manner that at least one of the signals is supplied also to the other circuit, the present invention prevents change of phase relation between the plural signals due to difference in wiring load, without directly processing the signals with higher power consumption. The first and second clock signals SCK1 and SCK2 are supplied to the first data signal line driving circuit SD1, while the first clock signal SCK1 is also supplied to the second data signal line driving circuit SD2 in parallel. The wirings 1 and 2 for the respective signals are adjusted to have equal wiring load with a dummy wiring 2 provided in the wiring 2, for solving uneven wiring load caused by difference of leading manner, the dummy wiring 2 constituting an additional capacitor section 7, together with a liquid crystal layer and a counter electrode.Type: GrantFiled: December 12, 2003Date of Patent: August 19, 2008Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Kazuhiro Maeda, Mamoru Onda
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Publication number: 20080167122Abstract: In a car racing game, one player is given a crown in racecourse units which indicates that the player is the fastest player (champion) of the racecourse. A player can play a crown competition with the player possessing the crown aiming to acquire the crown. For example, when a player Px challenges the crown of the racecourse 1, the player Px operates a player's car PC and plays a match against a player Pa who is a crown-possessing player of the racecourse 1. Specifically, the player Px plays a match against a ghost car GC controlled based on ghost data Ga1 of the player Pa for the racecourse 1. When the player Px has won the match, the crown of the racecourse 1 possessed by the player Pa is transferred to (acquired by) the player Px.Type: ApplicationFiled: December 13, 2007Publication date: July 10, 2008Applicant: NAMCO BANDAI GAMES INC.Inventors: Kazuhiro Maeda, Masaki Uchida, Kei Kobayashi
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Publication number: 20080167121Abstract: When a player Pa plays a ghost match against a player Pb, a player's car PC is controlled based on the operation of the player Pa, and a ghost car GC is computer-controlled based on ghost data Gb which is the previous play data of the player Pb. When the player Pa has won the match, the winning player Pa is added to a revenge list of the player Pb as a revenge target player. When the player Pb then plays the game, the player Pb is notified that the ghost car GC of the player Pb has been defeated by the player Pa on the revenge list.Type: ApplicationFiled: December 13, 2007Publication date: July 10, 2008Applicant: NAMCO BANDAI GAMES INC.Inventors: Kazuhiro Maeda, Masaki Uchida, Yoshikazu Takenaka, Tetsuo Takahashi, Yuuki Nagamatsu, Kei Kobayashi
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Patent number: 7365727Abstract: A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease.Type: GrantFiled: February 25, 2004Date of Patent: April 29, 2008Assignee: Sharp Kabushiki KaishaInventors: Masakazu Satoh, Yasushi Kubota, Hajime Washio, Kazuhiro Maeda, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 7339570Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.Type: GrantFiled: May 9, 2001Date of Patent: March 4, 2008Assignee: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Michael James Brownlow, Graham Andrew Cairns, Yasuyoshi Kaise, Kazuhiro Maeda
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Patent number: 7333096Abstract: A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.Type: GrantFiled: December 11, 2002Date of Patent: February 19, 2008Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Yasuyoshi Kaise, Sachio Tsujino, Kazuhiro Maeda, Keiji Takahashi, Yasushi Kubota, Toshiya Aoki
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Publication number: 20080036753Abstract: An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame.Type: ApplicationFiled: August 2, 2007Publication date: February 14, 2008Inventors: Hajime Washio, Yasuyoshi Kaise, Sachio Tsujino, Kazuhiro Maeda, Keiji Takahashi, Yasushi Kubota, Toshiya Aoki
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Patent number: 7286979Abstract: The communication terminal is comprised of: a voice input unit for inputting voice; a voice converting unit for converting the voice inputted into a voice signal; a character converting unit for converting the voice signal into a character signal; a transmitting unit capable of transmitting both the voice signal and the character signal via a communication line; and a control unit for controlling the transmitting unit in such a manner that the transmitting unit transmits the voice signal, or the character signal in response to a condition of the communication line. Also, the communication terminal is comprised of: a receiving unit capable of receiving both a voice signal and a character signal; an output unit for outputting the voice signal received by the receiving unit; and a display unit for displaying thereon the character signal received by the receiving unit.Type: GrantFiled: July 8, 2003Date of Patent: October 23, 2007Assignee: Hitachi, Ltd.Inventors: Kazuhiro Maeda, Shoichirou Funato, Toshio Kamimura
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Publication number: 20070146354Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.Type: ApplicationFiled: December 5, 2006Publication date: June 28, 2007Applicant: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Michael Brownlow, Graham Cairns, Yasuyoshi Kaise, Kazuhiro Maeda
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Patent number: 7213674Abstract: A transmission apparatus of an all-terrain vehicle includes: a non-stage transmission; a forward and backward movement switching device capable of switching to a forward movement position, a neutral position, or a backward movement position; and a shift operation device of rotary type for switching forward and backward movement disposed on a handle bar at a position adjacent to a handle grip. The shift operation device includes a rotary member for a shift operation and a locking mechanism for locking the rotary member so as not to move toward at least a position for backward movement from a position for neutral. The locking mechanism is configured to be handled by a hand griping the handle grip to make the locking mechanism unlocked.Type: GrantFiled: November 12, 2003Date of Patent: May 8, 2007Assignees: Kawasaki Jukogyo Kabushiki Kaisha, Asashi Denso Co., Ltd.Inventors: Kazuhiro Maeda, Koji Watanabe, Eiichi Tamaki
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Patent number: 7212184Abstract: In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.Type: GrantFiled: March 12, 2004Date of Patent: May 1, 2007Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 7202846Abstract: A data signal line drive circuit is provided with: a shift register belonging to a system, whose stages correspond to respective sampling units for driving odd-number-th data signal lines; and a shift register belonging to another system, whose stages correspond to respective sampling units for driving even-number-th data signal lines. On the occasion of low-resolution mode, only either of the shift registers is operated, and in accordance with the outputs from the respective stages of the shift register which has been operated, timing signals, which are supplied to the sampling units corresponding to the stages of both shift registers, are generated. With this arrangement, even if one of input signals each having different signal line resolution is inputted, a signal line drive circuit which consumes a small amount of electric power can be realized, while it is possible to specify the timings of the operation of signal line drive sections for driving signal lines, in accordance with the input signal.Type: GrantFiled: May 15, 2003Date of Patent: April 10, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazuhiro Maeda, Sachio Tsujino, Keiji Takahashi, Hajime Washio
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Patent number: 7196699Abstract: A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts.Type: GrantFiled: February 16, 2000Date of Patent: March 27, 2007Assignee: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Ichiro Shiraki, Kazuhiro Maeda, Yasuyoshi Kaise
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Patent number: 7190338Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.Type: GrantFiled: March 25, 2005Date of Patent: March 13, 2007Assignee: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Michael James Brownlow, Graham Andrew Cairns, Yasuyoshi Kaise, Kazuhiro Maeda