Patents by Inventor Kazumasa Nomoto

Kazumasa Nomoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210268822
    Abstract: A reversible recording medium according to an embodiment of the present disclosure includes: a recording layer including a leuco pigment as a coloring compound; and a first barrier film that is provided on one surface and a side surface of the recording layer and suppresses mixing of at least one of water or oxygen.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 2, 2021
    Inventors: Hiroshi MIZUNO, Hirohisa AMAGO, Kazumasa NOMOTO, Nobukazu HIRAI, Takehisa ISHIDA
  • Patent number: 8853017
    Abstract: An organic thin film transistor is disclosed, including a substrate formed of an organic insulating layer, a first layer deposited on the substrate using a plating technique to be used for forming a source electrode and a drain electrode, a second layer of a metal material deposited covering the first layer using a further plating technique to be used for forming the source electrode and the drain electrode with the metal material capable of forming an ohmic contact with an organic semiconductor material lower than the first layer, and an organic semiconductor layer over a region between the source electrode and the drain electrode, which are each formed with the first layer and the second layer. Also disclosed is an electric device provided with the organic thin film transistor.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: October 7, 2014
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Nobuhide Yoneya, Takahiro Ohe
  • Patent number: 8350255
    Abstract: A method for manufacturing a thin film transistor includes the steps of covering a gate electrode patterned on a substrate with a gate insulating film, forming an organic semiconductor layer and an electrode film on the gate insulating film in that lamination order, and forming a negative type photoresist film on the substrate provided with the organic semiconductor layer and the electrode film and forming a resist pattern, which serves as a mask for forming a source-drain by etching the electrode film, through back surface exposure from the substrate side by using the gate electrode as a light-shielding mask and the following development treatment.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 8, 2013
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Mao Katsuhara, Akira Yumoto
  • Publication number: 20130005120
    Abstract: An organic thin film transistor including a substrate with an organic insulating layer; a source and drain electrode layer electro deposited on the substrate; a second metal material source and drain electrode layer covering the first layer, the metal material capable of forming an ohmic contact with an organic semiconductor material lower than the first layer; and an organic semiconductor layer over a region between the source electrode and the drain electrode
    Type: Application
    Filed: September 12, 2012
    Publication date: January 3, 2013
    Applicant: SONY CORPORATION
    Inventors: Kazumasa Nomoto, Nobuhide Yoneya, Takahiro Ohe
  • Publication number: 20120326154
    Abstract: A method of making a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, which includes the steps of pattern coating a gate electrode material on the gate insulating film by printing; and carrying out a heat treatment to form the gate electrode resulting from drying for solidification of the pattern coated gate electrode material.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Applicant: SONY CORPORATION
    Inventors: Noriyuki Kawashima, Kazumasa Nomoto, Akihiro Nomoto
  • Patent number: 8283200
    Abstract: A manufacturing method of a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, which includes the steps of pattern coating a gate electrode material on the gate insulating film by printing; and carrying out a heat treatment to form the gate electrode resulting from drying for solidification of the pattern coated gate electrode material.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: October 9, 2012
    Assignee: Sony Corporation
    Inventors: Noriyuki Kawashima, Kazumasa Nomoto, Akihiro Nomoto
  • Patent number: 7985694
    Abstract: A method for forming a pattern includes the step of forming an electrically conductive film by applying a liquid composition onto a first plate. The liquid composition includes an organic solvent and conductive particles surface-modified with a fatty acid or an aliphatic amine. Then, a second pattern, which is a reverse pattern of a first pattern, is formed on the first plate by pressing a second plate having a concave-convex pattern on a surface thereof on a surface of the first plate having the electrically conductive film on the surface thereof. Then, the first pattern of the electrically conductive film is transferred onto convex top faces of the second plate. Then, the second pattern is transferred onto a surface of a transfer substrate by pressing the surface of the first plate having the second pattern thereon on the surface of the transfer substrate.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: July 26, 2011
    Assignee: Sony Corporation
    Inventors: Akhiro Nomoto, Kazumasa Nomoto, Toshio Fukuda
  • Patent number: 7863600
    Abstract: A field-effect transistor is provided. The field-effect transistor includes a gate electrode, a gate-insulating layer, source/drain electrodes, and an organic semiconductor layer constituting a channel region. The source/drain electrodes each include a conductive portion composed of a metal and an organic conductive material layer which at least partially covers the conductive portion and which is doped with a dopant. The channel region is composed of the organic semiconductor layer located between the source/drain electrodes. The channel region and each of the conductive portions is electrically connected through the organic conductive material layer.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: January 4, 2011
    Assignee: Sony Corporation
    Inventor: Kazumasa Nomoto
  • Publication number: 20100264410
    Abstract: A method for manufacturing a thin film transistor includes the steps of covering a gate electrode patterned on a substrate with a gate insulating film, forming an organic semiconductor layer and an electrode film on the gate insulating film in that lamination order, and forming a negative type photoresist film on the substrate provided with the organic semiconductor layer and the electrode film and forming a resist pattern, which serves as a mask for forming a source-drain by etching the electrode film, through back surface exposure from the substrate side by using the gate electrode as a light-shielding mask and the following development treatment.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 21, 2010
    Applicant: SONY CORPORATION
    Inventors: Kazumasa Nomoto, Mao Katsuhara, Akira Yumoto
  • Patent number: 7718465
    Abstract: A semiconductor device and process for producing same are provided. The process for producing a semiconductor device includes a first embossing step of pressing a stamp having a relief pattern onto a surface of a substrate to form a depression pattern on the surface of the substrate; a second step of feeding an application material composed of a semiconductor material or a conductive material into the depression pattern by printing; and a third step of curing the application material fed by printing.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: May 18, 2010
    Assignee: Sony Corporation
    Inventor: Kazumasa Nomoto
  • Publication number: 20100078639
    Abstract: The present invention provides a method for making a thin film semiconductor device having a bottom-gate, bottom-contact-type thin film transistor structure finer in size with satisfactory characteristics, in which the interface between a gate insulating film and a thin film semiconductor layer can be maintained at satisfactory conditions without being affected by formation of source/drain electrodes. A first gate insulating film (7-1) covering a gate electrode (5) on a substrate (3) is formed, and a pair of source/drain electrodes (9) is formed on the first gate insulating film (7-1). Subsequently, a second gate insulating film (7-2) is selectively formed only on the first gate insulating film (7-2) exposed from the source/drain electrodes (9). Next, a thin film semiconductor layer (11) continuously covering from the source/drain electrodes (9) to the first gate insulating film (7-1) through the second gate insulating film (7-2) is formed while making contact with the source/drain electrodes (9).
    Type: Application
    Filed: January 28, 2008
    Publication date: April 1, 2010
    Applicants: SONY CORPORATION, RIKEN
    Inventors: Kazumasa Nomoto, Nobukazu Hirai, Ryoichi Yasuda, Takeo Minari, Kazuhito Tsukagoshi, Yoshinobu Aoyagi
  • Publication number: 20100032660
    Abstract: An organic thin film transistor is disclosed, including a substrate formed of an organic insulating layer, a first layer deposited on the substrate using a plating technique to be used for forming a source electrode and a drain electrode, a second layer of a metal material deposited covering the first layer using a further plating technique to be used for forming the source electrode and the drain electrode with the metal material capable of forming an ohmic contact with an organic semiconductor material lower than the first layer, and an organic semiconductor layer over a region between the source electrode and the drain electrode, which are each formed with the first layer and the second layer. Also disclosed is an electric device provided with the organic thin film transistor.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 11, 2010
    Applicant: SONY CORPORATION
    Inventors: Kazumasa Nomoto, Nobuhide Yoneya, Takahiro Ohe
  • Publication number: 20090152540
    Abstract: A semiconductor device and process for producing same are provided. The process for producing a semiconductor device includes a first embossing step of pressing a stamp having a relief pattern onto a surface of a substrate to form a depression pattern on the surface of the substrate; a second step of feeding an application material composed of a semiconductor material or a conductive material into the depression pattern by printing; and a third step of curing the application material fed by printing.
    Type: Application
    Filed: February 17, 2009
    Publication date: June 18, 2009
    Applicant: Sony Corporation
    Inventor: Kazumasa Nomoto
  • Publication number: 20080251844
    Abstract: A method for forming a pattern includes the step of forming an electrically conductive film by applying a liquid composition onto a first plate. The liquid composition includes an organic solvent and conductive particles surface-modified with a fatty acid or an aliphatic amine. Then, a second pattern, which is a reverse pattern of a first pattern, is formed on the first plate by pressing a second plate having a concave-convex pattern on a surface thereof on a surface of the first plate having the electrically conductive film on the surface thereof. Then, the first pattern of the electrically conductive film is transferred onto convex top faces of the second plate. Then, the second pattern is transferred onto a surface of a transfer substrate by pressing the surface of the first plate having the second pattern thereon on the surface of the transfer substrate.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 16, 2008
    Applicant: SONY CORPORATION
    Inventors: Akihiro Nomoto, Kazumasa Nomoto, Toshio Fukuda
  • Publication number: 20080164463
    Abstract: A manufacturing method of a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, which includes the steps of pattern coating a gate electrode material on the gate insulating film by printing; and carrying out a heat treatment to form the gate electrode resulting from drying for solidification of the pattern coated gate electrode material.
    Type: Application
    Filed: May 10, 2007
    Publication date: July 10, 2008
    Applicant: SONY CORPORATION
    Inventors: Noriyuki Kawashima, Kazumasa Nomoto, Akihiro Nomoto
  • Patent number: 7259433
    Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: August 21, 2007
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Hiroshi Aozasa, Ichiro Fujiwara, Shinji Tanaka
  • Patent number: 7227255
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: June 5, 2007
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Patent number: 7199303
    Abstract: An optical energy conversion apparatus 10 includes a first impurity doped semiconductor layer 5, formed on a substrate, and which is of a semiconductor material admixed with a first impurity, an optically active layer 6, formed on the first impurity doped semiconductor layer 5, and which is of a hydrogen-containing amorphous semiconductor material, and a second impurity doped semiconductor layer 7, admixed with a second impurity and formed on the optically active semiconductor layer 6. The second impurity doped semiconductor layer is of a polycrystallized semiconductor material lower in hydrogen concentration than the material of the optically active semiconductor layer 6. The average crystal grain size in the depth-wise direction in an interfacing structure between the optically active semiconductor layer 6 and the second impurity doped semiconductor layer 7 is decreased stepwise in a direction proceeding from the surface of the second impurity doped semiconductor layer towards the substrate 1.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: April 3, 2007
    Assignee: Sony Corporation
    Inventors: Akio Machida, Setsuo Usui, Kazumasa Nomoto
  • Publication number: 20070026554
    Abstract: A semiconductor device and process for producing same are provided. The process for producing a semiconductor device includes a first embossing step of pressing a stamp having a relief pattern onto a surface of a substrate to form a depression pattern on the surface of the substrate; a second step of feeding an application material composed of a semiconductor material or a conductive material into the depression pattern by printing; and a third step of curing the application material fed by printing.
    Type: Application
    Filed: July 19, 2006
    Publication date: February 1, 2007
    Applicant: SONY CORPORATION
    Inventor: Kazumasa Nomoto
  • Patent number: 7074675
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: July 11, 2006
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi