Patents by Inventor Kazumasa Nomoto
Kazumasa Nomoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6891262Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.Type: GrantFiled: July 17, 2002Date of Patent: May 10, 2005Assignee: Sony CorporationInventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
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Publication number: 20050092358Abstract: An optical energy conversion apparatus 10 includes a first impurity doped semiconductor layer 5, formed on a substrate, and which is of a semiconductor material admixed with a first impurity, an optically active layer 6, formed on the first impurity doped semiconductor layer 5, and which is of a hydrogen-containing amorphous semiconductor material, and a second impurity doped semiconductor layer 7, admixed with a second impurity and formed on the optically active semiconductor layer 6. The second impurity doped semiconductor layer is of a polycrystallized semiconductor material lower in hydrogen concentration than the material of the optically active semiconductor layer 6. The average crystal grain size in the depth-wise direction in an interfacing structure between the optically active semiconductor layer 6 and the second impurity doped semiconductor layer 7 is decreased stepwise in a direction proceeding from the surface of the second impurity doped semiconductor layer towards the substrate 1.Type: ApplicationFiled: November 29, 2004Publication date: May 5, 2005Inventors: Akio Machida, Setsuo Usui, Kazumasa Nomoto
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Patent number: 6885060Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.Type: GrantFiled: March 19, 2002Date of Patent: April 26, 2005Assignee: Sony CorporationInventors: Kazumasa Nomoto, Toshio Kobayashi
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Publication number: 20050036391Abstract: A nonvolatile semiconductor memory apparatus capable of attaining a low voltage when writing data, wherein charge injection into an unnecessary portion is not performed when reading, and capable of unifying a threshold voltage level when erasing, comprising a first conductive type semiconductor region, two source/drain regions made by a second conductive type semiconductor, a plurality of dielectric films stacked on a first conductive type semiconductor region between the two source/drain regions, and a gate electrode; wherein the first conductive type semiconductor region between the two source/drain regions includes a first region wherein a channel is formed by an inversion layer of a minority carrier and a second region formed between the first region and a source/drain region on one side of the first region and having higher concentration than that of the first region.Type: ApplicationFiled: December 23, 2003Publication date: February 17, 2005Inventors: Hideto Tomiie, Shinji Satoh, Kazumasa Nomoto
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Patent number: 6794673Abstract: An amorphous silicon thin film includes a plastic substrate as a base, and insulating layers are formed thereon each radiated with a pulse laser beam which removes volatile contaminants like a resist as a pretreatment. A protective layer including a gas barrier layer and a refractory buffer layer is formed on the substrate. Gas penetration from the substrate to the amorphous silicon film is thereby prevented. Conduction of heat produced by energy beam radiation to the substrate is prevented as well. it is possible to increase energy intensity of energy beam radiated for the polycrystallization of the amorphous silicon film to the optimal value for perfect polycrystallization.Type: GrantFiled: December 11, 2001Date of Patent: September 21, 2004Assignee: Sony CorporationInventors: Dharam Pal Gosain, Jonathan Westwater, Miyako Nakagoe, Setsuo Usui, Kazumasa Nomoto
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Patent number: 6645837Abstract: A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.Type: GrantFiled: May 31, 2001Date of Patent: November 11, 2003Assignee: Sony CorporationInventors: Dharam Pal Gosain, Kazumasa Nomoto, Akio Machida, Miyako Nakagoe, Setsuo Usui
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Publication number: 20030136440Abstract: An optical energy conversion apparatus 10 includes a first impurity doped semiconductor layer 5, formed on a substrate, and which is of a semiconductor material admixed with a first impurity, an optically active layer 6, formed on the first impurity doped semiconductor layer 5, and which is of a hydrogen-containing amorphous semiconductor material, and a second impurity doped semiconductor layer 7, admixed with a second impurity and formed on the optically active semiconductor layer 6. The second impurity doped semiconductor layer is of a polycrystallized semiconductor material lower in hydrogen concentration than the material of the optically active semiconductor layer 6. The average crystal grain size in the depth-wise direction in an interfacing structure between the optically active semiconductor layer 6 and the second impurity doped semiconductor layer 7 is decreased stepwise in a direction proceeding from the surface of the second impurity doped semiconductor layer towards the substrate 1.Type: ApplicationFiled: December 19, 2002Publication date: July 24, 2003Inventors: Akio Machida, Setsuo Usui, Kazumasa Nomoto
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Publication number: 20030127680Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.Type: ApplicationFiled: December 20, 2002Publication date: July 10, 2003Inventors: Kazumasa Nomoto, Noriyuki Kawashima, Ichiro Fujiwara, Kenichi Taira
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Publication number: 20030122204Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.Type: ApplicationFiled: November 12, 2002Publication date: July 3, 2003Inventors: Kazumasa Nomoto, Hiroshi Aozasa, Ichiro Fujiwara, Shinji Tanaka
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Patent number: 6525379Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.Type: GrantFiled: July 31, 2001Date of Patent: February 25, 2003Assignee: Sony CorporationInventors: Kazumasa Nomoto, Noriyuki Kawashima, Ichiro Fujiwara, Kenichi Taira
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Publication number: 20030025147Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.Type: ApplicationFiled: July 17, 2002Publication date: February 6, 2003Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
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Patent number: 6461917Abstract: A memory device, a manufacturing method thereof, and an integrated circuit thereof are provided for storing information over a long period of time even if the memory device is manufactured at low temperatures. On a substrate made of glass, etc., a memory transistor and a selection transistor are formed, with a silicon nitride film and a silicon dioxide film in between. The memory transistor and the selection transistor are connected in series at a second impurity region. The conduction region for memory of the memory transistor is made of non-single crystal silicon and a storage region comprises a plurality of dispersed particulates made of non-single crystal silicon. Therefore, electrical charges can be stored partially if a tunnel insulating film has any defects. The tunnel insulating film is formed by exposing the surface of the conduction region for memory to the ionized gas containing oxygen atoms.Type: GrantFiled: June 25, 2001Date of Patent: October 8, 2002Assignee: Sony CorporationInventors: Kazumasa Nomoto, Dharam Pal Gosain, Setsuo Usui, Takashi Noguchi
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Publication number: 20020137288Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.Type: ApplicationFiled: March 19, 2002Publication date: September 26, 2002Inventors: Kazumasa Nomoto, Toshio Kobayashi
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Publication number: 20020089012Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.Type: ApplicationFiled: July 31, 2001Publication date: July 11, 2002Inventors: Kazumasa Nomoto, Noriyuki Kawashima, Ichiro Fujiwara, Kenichi Taira
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Publication number: 20020068390Abstract: A method is provided for forming a semiconductor thin film which is free from damage to the film with radiation of a pulse laser beam with the optimum energy value for perfect polycrystallization. For forming an amorphous silicon thin film, a surface of a plastic substrate as a base and insulating layers are each radiated with a pulse laser beam for removing volatile contaminants like a resist as a pretreatment. Damage to the film caused by a gas emitted from the base substrate and the insulating layers resulting from volatile contaminants is thus prevented. A protective layer including a gas barrier layer and a refractory buffer layer is formed on the substrate. Gas penetration from the substrate to the amorphous silicon film is thereby prevented. Conduction of heat produced by energy beam radiation to the substrate is prevented as well.Type: ApplicationFiled: December 11, 2001Publication date: June 6, 2002Inventors: Dharam Pal Gosain, Jonathan Westwater, Miyako Nakagoe, Setsuo Usui, Kazumasa Nomoto
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Publication number: 20020048869Abstract: A method is provided for forming a semiconductor thin film which is free from damage to the film with radiation of a pulse laser beam with the optimum energy value for perfect polycrystallization. For forming an amorphous silicon thin film, a surface of a plastic substrate as a base and insulating layers are each radiated with a pulse laser beam for removing volatile contaminants like a resist as a pretreatment. Damage to the film caused by a gas emitted from the base substrate and the insulating layers resulting from volatile contaminants is thus prevented. A protective layer including a gas barrier layer and a refractory buffer layer is formed on the substrate. Gas penetration from the substrate to the amorphous silicon film is thereby prevented. Conduction of heat produced by energy beam radiation to the substrate is prevented as well.Type: ApplicationFiled: July 16, 1998Publication date: April 25, 2002Inventors: DHARAM PAL GOSAIN, JONATHAN WESTWATER, MIYAKO NAKAGOE, SETSUO USUI, KAZUMASA NOMOTO
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Patent number: 6376290Abstract: A method is provided for forming a semiconductor thin film which is free from damage to the film with radiation of a pulse laser beam with the optimum energy value for perfect polycrystallization. For forming an amorphous silicon thin film, a surface of a plastic substrate as a base and insulating layers are each radiated with a pulse laser beam for removing volatile contaminants like a resist as a pretreatment. Damage to the film caused by a gas emitted from the base substrate and the insulating layers resulting from volatile contaminants is thus prevented. A protective layer including a gas barrier layer and a refractory buffer layer is formed on the substrate. Gas penetration from the substrate to the amorphous silicon film is thereby prevented. Conduction of heat produced by energy beam radiation to the substrate is prevented as well.Type: GrantFiled: July 16, 1998Date of Patent: April 23, 2002Assignee: Sony CorporationInventors: Dharam Pal Gosain, Jonathan Westwater, Miyako Nakagoe, Setsuo Usui, Kazumasa Nomoto
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Publication number: 20020016027Abstract: A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.Type: ApplicationFiled: May 31, 2001Publication date: February 7, 2002Inventors: Dharam Pal Gosain, Kazumasa Nomoto, Akio Machida, Miyako Nakagoe, Setsuo Usui
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Publication number: 20010044185Abstract: A memory device, a manufacturing method thereof, and an integrated circuit thereof are provided for storing information over a long period of time even if the memory device is manufactured at low temperatures. On a substrate made of glass, etc., a memory transistor and a selection transistor are formed, with a silicon nitride film and a silicon dioxide film in between. The memory transistor and the selection transistor are connected in series at a second impurity region. The conduction region for memory of the memory transistor is made of non-single crystal silicon and a storage region comprises a plurality of dispersed particulates made of non-single crystal silicon. Therefore, electrical charges can be stored partially if a tunnel insulating film has any defects. The tunnel insulating film is formed by exposing the surface of the conduction region for memory to the ionized gas containing oxygen atoms.Type: ApplicationFiled: June 25, 2001Publication date: November 22, 2001Applicant: Sony CorporationInventors: Kazumasa Nomoto, Dharam Pal Gosain, Setsuo Usui, Takashi Noguchi
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Patent number: 6320216Abstract: It is made possible to conduct writing and erasing information at high speed with a low gate voltage, to attain high integration with reduced power dissipation and to retain information accurately. A barrier layer, a transition layer, a barrier layer, a transition layer, a barrier layer, a charge accumulation layer and a barrier layer are stacked one after another on a conduction layer to cause transition of charges in the conduction layer to the charge accumulation layer by resonance tunneling. The conduction layer, the transition layers, and the charge accumulation layer are respectively made of Si. The barrier layers are respectively made of SiO2 so that electron affinity is made large and small alternately between those layers. Each capacitance respectively of the barrier layers is made smaller than e2/kBT so that charge transition does not occur according to the Coulomb blockade effect even if a voltage within a predetermined range is applied.Type: GrantFiled: December 8, 1998Date of Patent: November 20, 2001Assignee: Sony CorporationInventor: Kazumasa Nomoto