Patents by Inventor Kazumasa Nomoto

Kazumasa Nomoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7057233
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: June 6, 2006
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Patent number: 7049655
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: May 23, 2006
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Patent number: 7049180
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: May 23, 2006
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Patent number: 7038271
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: May 2, 2006
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Patent number: 7034356
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: April 25, 2006
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Patent number: 7023061
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: April 4, 2006
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Patent number: 7012329
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: March 14, 2006
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Publication number: 20060027860
    Abstract: A field-effect transistor is provided. The field-effect transistor includes a gate electrode, a gate-insulating layer, source/drain electrodes, and an organic semiconductor layer constituting a channel region. The source/drain electrodes each include a conductive portion composed of a metal and an organic conductive material layer which at least partially covers the conductive portion and which is doped with a dopant. The channel region is composed of the organic semiconductor layer located between the source/drain electrodes. The channel region and each of the conductive portions is electrically connected through the organic conductive material layer.
    Type: Application
    Filed: July 20, 2005
    Publication date: February 9, 2006
    Inventor: Kazumasa Nomoto
  • Publication number: 20050255652
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Application
    Filed: April 5, 2005
    Publication date: November 17, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Patent number: 6963107
    Abstract: A nonvolatile semiconductor memory apparatus capable of attaining a low voltage when writing data, wherein charge injection into an unnecessary portion is not performed when reading, and capable of unifying a threshold voltage level when erasing, comprising a first conductive type semiconductor region, two source/drain regions made by a second conductive type semiconductor, a plurality of dielectric films stacked on a first conductive type semiconductor region between the two source/drain regions, and a gate electrode; wherein the first conductive type semiconductor region between the two source/drain regions includes a first region wherein a channel is formed by an inversion layer of a minority carrier and a second region formed between the first region and a source/drain region on one side of the first region and having higher concentration than that of the first region.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: November 8, 2005
    Assignee: Sony Corporation
    Inventors: Hideto Tomiie, Shinji Satoh, Kazumasa Nomoto
  • Publication number: 20050230766
    Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.
    Type: Application
    Filed: May 18, 2005
    Publication date: October 20, 2005
    Inventors: Kazumasa Nomoto, Hiroshi Aozasa, Ichiro Fujiwara, Shinji Tanaka
  • Publication number: 20050218522
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Application
    Filed: April 5, 2005
    Publication date: October 6, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Publication number: 20050194627
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Application
    Filed: March 30, 2005
    Publication date: September 8, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Publication number: 20050189570
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Application
    Filed: April 5, 2005
    Publication date: September 1, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Publication number: 20050167735
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 4, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Publication number: 20050167737
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 4, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Publication number: 20050167736
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 4, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Publication number: 20050145898
    Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.
    Type: Application
    Filed: January 26, 2005
    Publication date: July 7, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi
  • Publication number: 20050146015
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Application
    Filed: March 7, 2005
    Publication date: July 7, 2005
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Patent number: 6906390
    Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: June 14, 2005
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Hiroshi Aozasa, Ichiro Fujiwara, Shinji Tanaka